REJ09B0178-0300
8
7534 Group
User's Manual
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 740 SERIES
Rev. 3.00 Revision date: Oct 23, 2006
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.
BEFORE USING THIS MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer to that chapter.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0 0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 3B 16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits
b1 b0
Function
0 0 : Single-chip mode 01: 10: Not available 11: 0 : 0 page 1 : 1 page
At reset
RW
0 0 0 0 0 1
Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock (XIN-XOUT) stop bit Internal system clock selection bit
0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release 0....... "0" at reset release 1....... "1" at reset release ?....... Undefined at reset release .......Contents determined by option at reset release Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows : R....... Read ...... Read enabled .......Read disabled W......Write ..... Write enabled ...... Write disabled ......."0" write
3. Supplementation
For details of software, refer to the "740 FAMILY SOFTWARE MANUAL." For details of development support tools, refer to the "Renesas Technology" Homepage (http://www.renesas.com).
Table of contents 7534 Group
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................... 2 FEATURES ......................................................................................................................................... 2 APPLICATION ................................................................................................................................... 2 PIN CONFIGURATION ..................................................................................................................... 2 FUNCTIONAL BLOCK ..................................................................................................................... 5 PIN DESCRIPTION ........................................................................................................................... 8 GROUP EXPANSION ....................................................................................................................... 9 FUNCTIONAL DESCRIPTION ....................................................................................................... 10 Central Processing Unit (CPU) ............................................................................................... 10 Memory ....................................................................................................................................... 14 I/O Ports ..................................................................................................................................... 16 Interrupts .................................................................................................................................... 20 Timers ......................................................................................................................................... 23 Serial Interface .......................................................................................................................... 25 A/D Converter ............................................................................................................................ 36 Reset Circuit .............................................................................................................................. 38 Clock Generating Circuit .......................................................................................................... 40 NOTES ON PROGRAMMING ........................................................................................................ 42 NOTES ON USE ............................................................................................................................. 42 DATA REQUIRED FOR MASK ORDERS ................................................................................... 43 FUNCTIONAL DESCRIPTION SUPPLEMENT ............................................................................ 45 Interrupt ...................................................................................................................................... 45 Timing After Interrupt ................................................................................................................ 46 A/D Converter ............................................................................................................................ 47 Stop mode .................................................................................................................................. 49 Wait mode .................................................................................................................................. 50 DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP ................................... 51 DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN ............................................................. 51 DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY ............................. 53
CHAPTER 2 APPLICATION
2.1 I/O port ........................................................................................................................................ 2 2.1.1 Memory map ...................................................................................................................... 2 2.1.2 Relevant registers ............................................................................................................. 2 2.1.3 Application example of key-on wake up ........................................................................ 6 2.1.4 Handling of unused pins .................................................................................................. 7 2.1.5 Notes on input and output pins ...................................................................................... 8 2.1.6 Termination of unused pins ............................................................................................. 9 2.2 Timer .......................................................................................................................................... 10 2.2.1 Memory map .................................................................................................................... 10 2.2.2 Relevant registers ........................................................................................................... 10 2.2.3 Timer application examples ........................................................................................... 16 2.3 Serial I/O ................................................................................................................................... 29 2.3.1 Memory map .................................................................................................................... 29 2.3.2 Relevant registers ........................................................................................................... 29 2.3.3 Serial I/O connection examples .................................................................................... 35
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2.3.4 Serial I/O transfer data format ...................................................................................... 37 2.3.5 Serial I/O application examples .................................................................................... 38 2.3.6 Notes on serial I/O ......................................................................................................... 49 2.4 USB ............................................................................................................................................ 50 2.4.1 Outline of USB ................................................................................................................ 50 2.4.2 Memory map .................................................................................................................... 56 2.4.3 Relevant registers ........................................................................................................... 57 2.4.4 USB application example ............................................................................................... 62 2.4.5 Notes concerning USB ................................................................................................... 69 2.5 A/D converter .......................................................................................................................... 71 2.5.1 Memory map .................................................................................................................... 71 2.5.2 Relevant registers ........................................................................................................... 71 2.5.3 A/D converter application examples ............................................................................. 75 2.5.4 Notes on A/D converter ................................................................................................. 77 2.6 Reset .......................................................................................................................................... 78 2.6.1 Connection example of reset IC ................................................................................... 78 _____________ 2.6.2 Notes on RESET pin ...................................................................................................... 78
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ........................................................................................................ 2 3.1.1 Absolute maximum ratings ............................................................................................... 2 3.1.2 Recommended operating conditions ............................................................................... 3 3.1.3 Electrical characteristics ................................................................................................... 4 3.1.4 A/D converter characteristics ........................................................................................... 5 3.1.5 Timing requirements ......................................................................................................... 6 3.1.6 Switching characteristics .................................................................................................. 6 3.2 Typical characteristics ............................................................................................................ 8 3.2.1 Power source current characteristic example (ICC-VCC characteristic) ........................ 8 3.2.2 VOH-IOH characteristic example ....................................................................................... 11 3.2.3 A/D conversion typical characteristics example .......................................................... 15 3.3 Notes on use ........................................................................................................................... 17 3.3.1 Notes on interrupts ......................................................................................................... 17 3.3.2 Notes on serial I/O ......................................................................................................... 18 3.3.3 Notes on A/D converter ................................................................................................. 19 3.3.4 Notes on _____________ timer ............................................................................................... 20 watchdog 3.3.5 Notes on RESET pin ...................................................................................................... 20 3.3.6 Notes on input and output pins .................................................................................... 20 3.3.7 Notes on programming ................................................................................................... 21 3.3.8 Programming and test of built-in PROM version ........................................................ 22 3.3.9 Notes on built-in PROM version ................................................................................... 23 3.3.10 Termination of unused pins ......................................................................................... 24 3.3.11 Notes on CPU mode register ...................................................................................... 25 3.3.12 Notes on using 32-pin version .................................................................................... 25 3.3.13 Electric characteristic differences among mask ROM and One TIme PROM version MCUs ... 25 3.3.14 Note on power source voltage .................................................................................... 25 3.3.15 USB communication ...................................................................................................... 26 3.4 Countermeasures against noise ......................................................................................... 27 3.4.1 Shortest wiring length ..................................................................................................... 27 3.4.2 Connection of bypass capacitor across VSS line and VCC line .................................. 29 3.4.3 Wiring to analog input pins ........................................................................................... 30
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Table of contents 7534 Group
3.4.4 Oscillator concerns .......................................................................................................... 30 3.4.5 Setup for I/O ports .......................................................................................................... 32 3.4.6 Providing of watchdog timer function by software ..................................................... 33 3.5 List of registers ...................................................................................................................... 34 3.6 Package outline ...................................................................................................................... 53 3.7 List of instruction code ........................................................................................................ 55 3.8 Machine instructions ............................................................................................................. 56 3.9 SFR memory map ................................................................................................................... 67 3.10 Pin configurations ................................................................................................................ 68
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List of figures 7534 Group
List of figures
CHAPTER 1 HARDWARE
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP .................................................... 2 2 Pin configuration of M37534M4-XXXGP, M37534E4GP .................................................. 3 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP ........................... 4 4 Functional block diagram (PRSP0036GA-A package type) ............................................. 5 5 Functional block diagram (PLQP0032GB-A package type) ............................................. 6 6 Functional block diagram (PRDP0042BA-A package type) ............................................. 7 7 Memory expansion plan ........................................................................................................ 9 8 740 Family CPU register structure .................................................................................... 10 9 Register push and pop at interrupt generation and subroutine call ............................ 11 10 Structure of CPU mode register ...................................................................................... 13 11 Switching method of CPU mode register ....................................................................... 13 12 Memory map diagram ....................................................................................................... 14 13 Memory map of special function register (SFR) ........................................................... 15 14 Structure of pull-up control register ................................................................................ 16 15 Structure of port P1P3 control register .......................................................................... 16 16 Block diagram of ports (1) ............................................................................................... 18 17 Block diagram of ports (2) ............................................................................................... 19 18 Interrupt control .................................................................................................................. 21 19 Structure of Interrupt-related registers ........................................................................... 21 20 Connection example when using key input interrupt and port P0 block diagram ... 22 21 Structure of timer X mode register ................................................................................. 23 22 Timer count source set register ...................................................................................... 23 23 Block diagram of timer X, timer 1 and timer 2 ............................................................. 24 24 Block diagram of UART serial I/O1 ................................................................................ 25 25 Operation of UART serial I/O1 function ......................................................................... 25 26 Continuous transmission operation of UART serial I/O ............................................... 26 27 USB mode block diagram ................................................................................................ 27 28 USB transceiver block diagram ....................................................................................... 27 29 Structure of serial I/Orelated registers (1) ..................................................................... 28 30 Structure of serial I/O1-related registers (2) ................................................................. 29 31 Structure of serial I/O1-related registers (3) ................................................................. 30 32 Structure of serial I/O1-related registers (4) ................................................................. 31 33 Structure of serial I/O1-related registers (5) ................................................................. 32 34 Structure of serial I/O2 control registers ........................................................................ 34 35 Block diagram of serial I/O2 ............................................................................................ 34 36 Serial I/O2 timing (LSB first) ........................................................................................... 35 37 Structure of A/D control register ..................................................................................... 36 38 Structure of A/D conversion register .............................................................................. 36 39 Block diagram of A/D converter ...................................................................................... 36 40 Block diagram of watchdog timer .................................................................................... 37 41 Structure of watchdog timer control register ................................................................. 37 42 Example of reset circuit .................................................................................................... 38 43 Timing diagram at reset ................................................................................................... 38 44 Internal status of microcomputer at reset ...................................................................... 39 45 External circuit of ceramic resonator .............................................................................. 40 46 External clock input circuit ............................................................................................... 40 47 Structure of MISRG ........................................................................................................... 40
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List of figures 7534 Group
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig.
48 49 50 51 52 53 54 55 56 57 58
Block diagram of system clock generating circuit (for ceramic resonator) ............... 41 Countermeasure (2) by software ..................................................................................... 43 Method to stabilize A/D conversion accuracy ............................................................... 43 Programming and testing of One Time PROM version ............................................... 44 Timing chart after an interrupt occurs ............................................................................ 46 Time up to execution of the interrupt processing routine ........................................... 46 A/D conversion equivalent circuit .................................................................................... 48 A/D conversion timing chart ............................................................................................. 48 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP ................... 53 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGP, M37534E4GP .................. 54 Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSS ........ 55
CHAPTER 2 APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory map of registers relevant to I/O port ............................................................ 2 2.1.2 Structure of Port Pi (i = 0 to 4) .................................................................................... 2 2.1.3 Structure of Port Pi direction register (i = 0 to 4) ..................................................... 3 2.1.4 Structure of Pull-up control register ............................................................................. 3 2.1.5 Structure of P1P3 control register ................................................................................ 4 2.1.6 Structure of Interrupt edge selection register ............................................................. 4 2.1.7 Structure of Interrupt request register 1 ...................................................................... 5 2.1.8 Structure of Interrupt control register 1 ....................................................................... 5 2.1.9 Relevant registers setting .............................................................................................. 6 2.1.10 Application circuit example .......................................................................................... 6 2.1.11 Control procedure .......................................................................................................... 7 2.2.1 Memory map of registers relevant to timers ............................................................. 10 2.2.2 Structure of Prescaler 12, Prescaler X ...................................................................... 10 2.2.3 Structure of Timer 1 ..................................................................................................... 11 2.2.4 Structure of Timer 2 ..................................................................................................... 11 2.2.5 Structure of Timer X ..................................................................................................... 12 2.2.6 Structure of Timer X mode register ............................................................................ 13 2.2.7 Structure of Timer count source set register ............................................................ 14 2.2.8 Structure of Interrupt edge selection register ........................................................... 14 2.2.9 Structure of Interrupt request register 1 .................................................................... 15 2.2.10 Structure of Interrupt control register 1 ................................................................... 15 2.2.11 Timers connection and setting of division ratios .................................................... 17 2.2.12 Relevant registers setting .......................................................................................... 18 2.2.13 Control procedure ........................................................................................................ 19 2.2.14 Peripheral circuit example .......................................................................................... 20 2.2.15 Timers connection and setting of division ratios .................................................... 20 2.2.16 Relevant registers setting .......................................................................................... 21 2.2.17 Control procedure ........................................................................................................ 22 2.2.18 Judgment method of valid/invalid of input pulses .................................................. 23 2.2.19 Relevant registers setting .......................................................................................... 24 2.2.20 Control procedure ........................................................................................................ 25 2.2.21 Timers connection and setting of division ratios .................................................... 26 2.2.22 Relevant registers setting .......................................................................................... 27 2.2.23 Control procedure ........................................................................................................ 28 2.3.1 Memory map of registers relevant to serial I/O ........................................................ 29 2.3.2 Structure of Transmit/Receive buffer register ........................................................... 29 2.3.3 Structure of UART status register .............................................................................. 30 2.3.4 Structure of Serial I/O1 control register ..................................................................... 30
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List of figures 7534 Group
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig.
2.3.5 Structure of UART control register ............................................................................. 31 2.3.6 Structure of Baud rate generator ................................................................................ 31 2.3.7 Structure of Serial I/O2 control register ..................................................................... 32 2.3.8 Structure of Serial I/O2 register .................................................................................. 32 2.3.9 Structure of Interrupt edge selection register ........................................................... 33 2.3.10 Structure of Interrupt request register 1 .................................................................. 33 2.3.11 Structure of Interrupt control register 1 ................................................................... 34 2.3.12 Serial I/O connection examples (1) .......................................................................... 35 2.3.13 Serial I/O connection examples (2) .......................................................................... 36 2.3.14 Serial I/O transfer data format .................................................................................. 37 2.3.15 Connection diagram .................................................................................................... 38 2.3.16 Timing chart ................................................................................................................. 38 2.3.17 Registers setting relevant to transmission side ...................................................... 39 2.3.18 Transmission data setting of serial I/O2 .................................................................. 40 2.3.19 Registers setting relevant to reception side ............................................................ 40 2.3.20 Control procedure of transmission side ................................................................... 41 2.3.21 Control procedure of reception side ......................................................................... 42 2.3.22 Connection diagram .................................................................................................... 43 2.3.23 Timing chart ................................................................................................................. 43 2.3.24 Registers setting relevant to transmission side ...................................................... 45 2.3.25 Registers setting relevant to reception side ............................................................ 46 2.3.26 Control procedure of transmission side ................................................................... 47 2.3.27 Control procedure of reception side ......................................................................... 48 2.3.28 Sequence of clearing serial I/O ................................................................................ 49 2.4.1 Communication sequence of USB .............................................................................. 51 2.4.2 Data structure of USB packet ..................................................................................... 52 2.4.3 USB (L.S.) interface ...................................................................................................... 55 2.4.4 USB (L.S.) connection example .................................................................................. 55 2.4.5 Memory map of registers relevant to USB ................................................................ 56 2.4.6 Description of the register structure ........................................................................... 57 2.4.7 Register structures relevant to USB (1) .................................................................... 58 2.4.8 Register structures relevant to USB (2) .................................................................... 59 2.4.9 Register structures relevant to USB (3) .................................................................... 60 2.4.10 Register structures relevant to USB (4) .................................................................. 61 2.4.11 Control method of control sequence ........................................................................ 62 2.4.12 Timing chart of the transaction according to each token ..................................... 63 2.4.13 USB interrupt processing example (OUT token) .................................................... 65 2.4.14 USB interrupt processing example (IN token) ........................................................ 66 2.4.15 Data read timing of SETUP token ............................................................................ 67 2.4.16 Data read timing of OUT token ................................................................................ 67 2.4.17 Data read timing of IN token (endpoint 0) and IN token (endpoint 1) token .... 67 2.4.18 Timing chart of each signal ....................................................................................... 68 2.4.19 Example for determination of resume interrupt ...................................................... 69 2.4.20 Processing for width of SE0 signal .......................................................................... 69 2.4.21 Countermeasure (2) by software .............................................................................. 70 2.5.1 Memory map of registers relevant to A/D converter ................................................ 71 2.5.2 Structure of A/D control register ................................................................................. 71 2.5.3 Structure of A/D conversion register (high-order) .................................................... 72 2.5.4 Structure of A/D conversion register (low-order) ...................................................... 72 2.5.5 Structure of Interrupt edge selection register ........................................................... 73 2.5.6 Structure of Interrupt request register 1 .................................................................... 73 2.5.7 Structure of Interrupt control register 1 ..................................................................... 74
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List of figures 7534 Group
Fig. Fig. Fig. Fig. Fig. Fig.
2.5.8 Connection diagram ...................................................................................................... 75 2.5.9 Relevant registers setting ............................................................................................ 75 2.5.10 Control procedure for 8-bit read ............................................................................... 76 2.5.11 Control procedure for 10-bit read ............................................................................. 76 2.5.12 Method to stabilize A/D conversion accuracy ......................................................... 77 2.6.1 Example of poweron reset circuit ............................................................................... 78
CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 Power source current measurement circuit in USB mode at oscillation stop ........ 5 3.1.2 Output switching characteristics measurement circuit ............................................... 6 3.1.3 Timing chart ..................................................................................................................... 7 3.2.1 ICC-VCC characteristic example (in double-speed mode) ............................................. 8 3.2.2 ICC-VCC characteristic example (at WIT instruction execution) .................................. 8 3.2.3 ICC-VCC characteristic example (At STP instruction execution, Ta = 25 C) ........... 9 3.2.4 ICC-VCC characteristic example (At STP instruction execution, Ta = 85 C) ........... 9 3.2.5 ICC-VCC characteristic example (at USB suspend, Ta = 25 C) .............................. 10 3.2.6 ICC-VCC characteristic example (A/D conversion executed/not executed, f(XIN) = 6MHz, in double-speed mode) ................................................................................................. 10 3.2.7 VOH-IOH characteristic example of P-channel (Ta = 25 C): normal port ............... 11 3.2.8 VOH-IOH characteristic example of P-channel (Ta = 85 C): normal port ............... 11 3.2.9 VOL-IOL characteristic example of N-channel (Ta = 25 C): Normal port ............... 12 3.2.10 VOL-IOL characteristic example of N-channel (Ta = 85 C): Normal port ............. 12 3.2.11 VOL-IOL characteristic example of N-channel (Ta = 25 C): LED drive port ........ 13 3.2.12 VOL-IOL characteristic example N-channel (Ta = 85 C): LED drive port ............. 13 3.2.13 "L" input current of port at pull-up transistor connected ....................................... 14 3.2.14 Definition of A/D conversion accuracy ..................................................................... 15 3.2.15 A/D conversion typical characteristic example ........................................................ 16 3.3.1 Sequence of switch the detection edge ..................................................................... 17 3.3.2 Sequence of check of interrupt request bit ............................................................... 17 3.3.3 Structure of interrupt control register 1 ..................................................................... 18 3.3.4 Sequence of clearing serial I/O .................................................................................. 18 3.3.5 Method to stabilize A/D conversion accuracy ........................................................... 19 3.3.6 Initialization of processor status register ................................................................... 21 3.3.7 Sequence of PLP instruction execution ..................................................................... 21 3.3.8 Stack memory contents after PHP instruction execution ........................................ 21 3.3.9 Status flag at decimal calculations ............................................................................. 22 3.3.10 Programming and testing of One Time PROM version ......................................... 22 3.3.11 Switching method of CPU mode register ................................................................ 25 3.3.12 Countermeasure (2) by software .............................................................................. 26 3.4.1 Selection of packages .................................................................................................. 27 _____________ 3.4.2 Wiring for the RESET pin ............................................................................................ 27 3.4.3 Wiring for clock I/O pins .............................................................................................. 28 3.4.4 Wiring for CNVSS pin ................................................................................................... 28 3.4.5 Wiring for the VPP pin of the One Time PROM ........................................................ 29 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................... 29 3.4.7 Analog signal line and a resistor and a capacitor ................................................... 30 3.4.8 Wiring for a large current signal line ......................................................................... 30 3.4.9 Wiring of signal lines where potential levels change frequently ............................ 31 3.4.10 VSS pattern on the underside of an oscillator .......................................................... 31 3.4.11 Setup for I/O ports ...................................................................................................... 32 3.4.12 Watchdog timer by software ...................................................................................... 33
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List of figures 7534 Group
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig.
3.5.1 Structure of Port Pi (i = 0 to 4) .................................................................................. 34 3.5.2 Structure of Port Pi direction register (i = 0 to 4) ................................................... 34 3.5.3 Structure of Pull-up control register ........................................................................... 35 3.5.4 Structure of Port P1P3 control register ..................................................................... 35 3.5.5 Structure of Transmit/Receive buffer register ........................................................... 36 3.5.6 Structure of UART status register .............................................................................. 36 3.5.7 Structure of USB status register ................................................................................. 37 3.5.8 Structure of Serial I/O1 control register ..................................................................... 38 3.5.9 Structure of UART control register ............................................................................. 38 3.5.10 Structure of Baud rate generator .............................................................................. 39 3.5.11 Structure of USB data toggle synchronization register ......................................... 39 3.5.12 Structure of USB interrupt source discrimination register 1 ................................. 39 3.5.13 Structure of USB interrupt source discrimination register 2 ................................. 40 3.5.14 Structure of USB interrupt control register .............................................................. 40 3.5.15 Structure of USB transmit data byte number set register 0 ................................. 41 3.5.16 Structure of USB transmit data byte number set register 1 ................................. 41 3.5.17 Structure of USB PID control register 0 .................................................................. 41 3.5.18 Structure of USB PID control register 1 .................................................................. 42 3.5.19 Structure of USB address register ........................................................................... 42 3.5.20 Structure of USB sequence bit initialization register ............................................. 42 3.5.21 Structure of USB control register ............................................................................. 42 3.5.22 Structure of Prescaler 12, Prescaler X .................................................................... 43 3.5.23 Structure of Timer 1 ................................................................................................... 43 3.5.24 Structure of Timer 2 ................................................................................................... 44 3.5.25 Structure of Timer X mode register ......................................................................... 45 3.5.26 Structure of Timer X ................................................................................................... 46 3.5.27 Structure of Timer count source set register .......................................................... 46 3.5.28 Structure of Serial I/O2 control register ................................................................... 47 3.5.29 Structure of Serial I/O2 register ................................................................................ 47 3.5.30 Structure of A/D control register ............................................................................... 48 3.5.31 Structure of A/D conversion register (high-order) .................................................. 49 3.5.32 Structure of A/D conversion register (low-order) .................................................... 49 3.5.33 Structure of MISRG .................................................................................................... 50 3.5.34 Structure of Watchdog timer control register .......................................................... 50 3.5.35 Structure of Interrupt edge selection register ......................................................... 51 3.5.36 Structure of CPU mode register ............................................................................... 51 3.5.37 Structure of Interrupt request register 1 .................................................................. 52 3.5.38 Structure of Interrupt control register 1 ................................................................... 52 3.10.1 M37534M4-XXXFP, M37534E8FP pin configuration .............................................. 68 3.10.2 M37534M4-XXXGP, M37534E4GP pin configuration ............................................. 69 3.10.3 M37534M4-XXXSP, M37534E8SP, M37534RSS pin configuration ...................... 70
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List of tables 7534 Group
List of tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description .................................................................................................................... 8 2 List of supported products ................................................................................................ 9 3 Push and pop instructions of accumulator or processor status register .................. 11 4 Set and clear instructions of each bit of processor status register .......................... 12 5 I/O port function table ...................................................................................................... 17 6 Interrupt vector address and priority ............................................................................. 20 7 Relation of the width of SE0 and the state of the device ......................................... 33 8 Special programming adapter ......................................................................................... 43 9 Interrupt sources, vector addresses and interrupt priority .......................................... 44 10 Change of A/D conversion register during A/D conversion ..................................... 46 11 Stop mode state ............................................................................................................. 48 12 Wait mode state ............................................................................................................. 49 13 Description of improved USB function for 7534 Group ............................................ 50 14 Differences among 32-pin, 36-pin and 42-pin ............................................................ 50 15 Differences among 32-pin, 36-pin and 42-pin (SFR) ................................................ 51
CHAPTER 2 APPLICATION
Table Table Table Table Table Table Table Table 2.1.1 2.2.1 2.3.1 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 Handling of unused pins ............................................................................................. 7 CNTR0 active edge switch bit function ................................................................... 13 Setting example of baud rate generator (BRG) and transfer bit rate values .... 44 Transfer types of USB ............................................................................................... 50 Packet types of USB ................................................................................................. 52 Data structure of USB packet .................................................................................. 53 PID ............................................................................................................................... 53 Special signal of USB ............................................................................................... 54
CHAPTER 3 APPENDIX
Table Table Table Table Table Table Table Table Table Table 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.3.1 3.3.2 3.5.1 Absolute maximum ratings .......................................................................................... 2 Recommended operating conditions .......................................................................... 3 Electrical characteristics (1) ........................................................................................ 4 Electrical characteristics (2) ........................................................................................ 5 A/D Converter characteristics (1) ............................................................................... 5 Timing requirements .................................................................................................... 6 Switching characteristics ............................................................................................. 6 Programming adapters .............................................................................................. 23 PROM programmer address setting ........................................................................ 24 CNTR0 active edge switch bit function ................................................................... 45
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CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USE DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
HARDWARE 7534 Group DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 7534 Group is the 8-bit microcomputer based on the 740 family core technology. The 7534 Group has a USB, 8-bit timers, and an A/D converter, and is useful for an input device for personal computer peripherals.
*
FEATURES
* * * * * *
Basic machine-language instructions ....................................... 69 The minimum instruction execution time .......................... 0.34 s (at 6 MHz oscillation frequency for the shortest instruction) Memory size ROM ............................................... 8K to 16K bytes RAM .............................................. 256 to 384 bytes Programmable I/O ports ...................................... 28 (36-pin type) ............................................................................ 24 (32-pin type) ............................................................................ 33 (42-pin type) Interrupts .................................................... 14 sources, 8 vectors Timers ............................................................................ 8-bit 3
* * * * * * *
Serial Interface Serial I/O1 ................................ used only for Low Speed in USB (based on Low-Speed USB2.0 specification) (USB/UART) Serial I/O2 ...................................................................... 8-bit 1 (Clock-synchronized) A/D converter ................................................ 10-bit 8 channels Clock generating circuit ............................................. Built-in type (connect to external ceramic resonator or quartz-crystal oscillator ) Watchdog timer ............................................................ 16-bit 1 Power source voltage At 6 MHz XIN oscillation frequency at ceramic resonator ................................ 4.1 to 5.5 V(4.4 to 5.25 V at USB operation) Power dissipation ............................................ 30 mW (standard) Operating temperature range ................................... -20 to 85 C (0 to 70 C at USB operation) Built-in USB 3.3 V Regulator + transceiver based on Low-Speed USB2.0 specification
APPLICATION
Input device for personal computer peripherals
PIN CONFIGURATION (TOP VIEW)
P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
P11/TXD/D+ P10/RXD/DP07 P06 P05 P04 P03 P02 P01 P00 USBVREFOUT P37/INT0 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
Outline: PRSP0036GA-A (36P2R-A)
Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP
M37534M4-XXXFP M37534E8FP
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HARDWARE 7534 Group PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
24
23
22
21
20
19
18
P07 P10/RXD/DP11/TXD/D+ P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1
17
P06 P05 P04 P03 P02 P01 P00 USBVREFOUT
25 26 27 28 29 30 31 32
16 15 14
M37534M4-XXXGP M37534E4GP
13 12 11 10 9
P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN
3
4
5
6
7
Outline PLQP0032GB-A (32P6U-A)
Fig. 2 Pin configuration of M37534M4-XXXGP, M37534E4GP
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P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC
1
2
8
HARDWARE 7534 Group PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
P14/CNTR0 P15 P16 P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 P40 P41 VREF RESET CNVSS Vcc XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P13/SDATA P12/SCLK P11/TXD/D+ P10/RXD/DP07 P06 P05 P04 P03 P02 P01 P00 USBVREFOUT P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
Outline 42S1M, PRDP0042BA-A (42P4B)
Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP
M37534RSS M37534M4-XXXSP M37534E8SP
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7534 Group
FUNCTIONAL BLOCK DIAGRAM (Package: PRSP0036GA-A)
Clock input VSS VCC
15 13 14 18
Clock output RESET CNVSS
Reset input
XIN
XOUT
12
25 24 23 22 21 20 19
11 10 9 8 7 6 5 4
26
3 2 1 36 35
34 33 32 31 30 29 28 27
VREF
FUNCTIONAL BLOCK
HARDWARE
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wake up
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FUNCTIONAL BLOCK
16
17
Fig. 4 Functional block diagram (PRSP0036GA-A package type)
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CPU
Clock generating circuit
RAM ROM
X Prescaler 12 (8) Prescaler X (8) S
CNTR0
A
Timer 1 (8) Timer 2 (8) Timer X (8)
Y
PC H PS
PCL
Watchdog timer
Reset
0
A/D converter (1 0 ) SI/O1(8) USB(LS) SI/O2(8)
USBVREFOUT
INT0
P3(7)
P2(8)
P1(5)
P0(8)
7534 Group
FUNCTIONAL BLOCK DIAGRAM (Package: PLQP0032GB-A)
Clock input VSS VCC
8 6 7 11
Clock output RESET CNVSS
Reset input
XIN
XOUT
5
16 15 14 13 12
4 3 2 1 32 31
17
30 29 28 27 26
25 24 23 22 21 20 19 18
VREF
HARDWARE
FUNCTIONAL BLOCK
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wake up
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CPU
9
10
Fig. 5 Functional block diagram (PLQP0032GB-A package type)
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Clock generating circuit
RAM ROM
X Prescaler 12 (8) Prescaler X (8) S
CNTR0
A
Timer 1 (8) Timer 2 (8) Timer X (8)
Y
PC H PS
PCL
Watchdog timer
Reset
0
A/D converter (1 0 ) SI/O1(8) USB(LS) SI/O2(8)
USBVREFOUT
P3(5)
P2(6)
P1(5)
P0(8)
7534 Group
FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0042BA-A)
Reset input VSS VCC
18 16 17 21
Clock input Clock output X IN X OUT RESET CNVSS
13 14
15
29 28 27 26 25 24 23 22
12 11 10 9 8
754
30
3
2
1 42 41 40 39
38 37 36 35 34 33 32 31
VREF
USBVREFOUT
FUNCTIONAL BLOCK
HARDWARE
I/O port P4
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wakeup
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CPU
19
20
Fig. 6 Functional block diagram (PRDP0042BA-A package type)
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Clock generating circuit
RAM ROM
X Prescaler 12 (8) Prescaler X (8) S PC H PS
CNTR0
A
Timer 1 (8) Timer 2 (8) Timer X (8)
Y
PCL
Watchdog timer
Reset
0
A/D converter (1 0 ) SI/O1(8) USB(LS)
SI/O2(8)
INT0 INT1
P4(2)
P3(8)
P2(8)
P1(7)
P0(8)
HARDWARE 7534 Group PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description Pin Name Vcc, Vss VREF USBVREFOUT CNVss RESET XIN XOUT P00-P07 Power source Analog reference voltage USB reference voltage output CNVss Reset input Clock input Clock output I/O port P0 Function expect a port function *Apply voltage of 4.1 to 5.5 V (4.4 to 5.25 V at USB operating) to Vcc, and 0 V to Vss. *Reference voltage input pin for A/D converter *Output pin for pulling up a D- line with 1.5 k external resistor *Chip operating mode control pin, which is always connected to Vss. *Reset input pin for active "L" *Input and output pins for main clock generating circuit *Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *8-bit I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS 3-state output structure at CMOS compatible input level *Whether a built-in pull-up resistor is to be used or not can be determined by program. P10/RxD/DP11/TxD/D+ P12/SCLK P13/SDATA P14/CNTR0 P15, P16 P20/AN0- P27/AN7 P30-P35 I/O port P3 I/O port P2 I/O port P1 *7-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS 3-state output structure at CMOS compatible input level *CMOS/TTL level can be switched for P10, P12, P13. *When using the USB function, input level of ports P10 and P11 becomes USB input level, and output level of them becomes USB output level. *8-bit I/O port having almost the same function as P0 *CMOS 3-state output structure at CMOS compatible input level *8-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS 3-state output structure at CMOS compatible input level (CMOS/TTL level can be switched for P36, P37). *P30 to P36 can output a large current for driving LED. P36/INT1 P37/INT0 P40, P41 I/O port P4 *Whether a built-in pull-up resistor is to be used or not can be determined by program. *2-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *Interrupt input pins *Input pins for A/D converter *Timer X function pin *Serial I/O1 function pin *Serial I/O2 function pin *Key-input (key-on wake up interrupt input) pins Function
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HARDWARE 7534 Group GROUP EXPANSION
GROUP EXPANSION
Renesas plans to expand the 7534 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU . Memory size ROM/PROM size .................................................. 8 K to 16 K bytes RAM size ................................................................ 256 to 384 bytes
Package PRSP0036GA-A ......................... 0.8 mm-pitch plastic molded SOP PLQP0032GB-A ........................ 0.8 mm-pitch plastic molded LQFP PRDP0042BA-A .................................... 42 pin plastic molded SDIP 42SIM ...................................... 42 pin shrink ceramic PIGGY BACK
ROM size (Byte)
16K
M37534E8
8K
M37534M4 M37534E4
0
Fig. 7 Memory expansion plan Currently supported products are listed below. Table 2 List of supported products Part number M37534M4-XXXFP M37534M4-XXXGP M37534M4-XXXSP M37534E4GP M37534E8FP M37534E8SP M37534RSS
128
256
384
RAM size (Byte)
(P) ROM size (bytes) ROM size for User () 8192 (8062) 8192 (8062) 8192 (8062) 8192 (8062) 16384 (16254) 16384 (16254)
RAM size (bytes) 256 256 256 256 384 384 384
Package PRSP0036GA-A PLQP0032GB-A PRDP0042BA-A PLQP0032GB-A PRSP0036GA-A PRDP0042BA-A 42S1M
Remarks Mask ROM version Mask ROM version Mask ROM version One Time PROM version (blank) One Time PROM version (blank) One Time PROM version (blank) Emulator MCU
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 7534 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instructions cannot be used. The MUL and DIV instructions cannot be used. The WIT and STP instructions can be used. The central processing unit (CPU) has the six registers.
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 9.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to "1", the value contained in index register X becomes the address for the second OPERAND.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
b7
b0
A
b7 b0
Accumulator Index Register X
b0
X
b7
Y
b7 b0
Index Register Y Stack Pointer
b0
S
b15 b7
PCH
b7
PCL
b0
Program Counter
N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag
Fig. 8 740 Family CPU register structure
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request (Note) Execute JSR M (S) Store Return Address on Stack (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1)
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S - 1) (PCL) (S - 1) (PS) (S - 1) Store Contents of Processor Status Register on Stack Store Return Address on Stack
Subroutine Execute RTS Restore Return Address (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) (S + 1) M (S)
I Flag "0" to "1" Fetch the Jump Vector
Restore Contents of Processor Status Register
Restore Return Address
Note : The condition to enable the interrupt
Interrupt enable bit is "1" Interrupt disable flag is "0"
Fig. 9 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
[CPU Mode Register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16.
b7
b0
CPU mode register (CPUM: address 003B16) Processor mode bits b1 b0 0 0 Single-chip mode 01 10 Not available 11 Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns "0" when read) (Do not write "1" to these bits ) Main clock division ratio selection bits b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f() = f(XIN) (Double-speed mode)
Fig. 10 Structure of CPU mode register Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method. Note on stack page When 1 page is used as stack area by the stack page selection bit, the area which can be used as stack depends on RAM size. Especially, be careful that the RAM area varies in Mask ROM version, One Time PROM version and Emulator MCU.
After releasing reset
Start with an on-chip oscillator (Note)
Wait until establish ceramic oscillator clock. Switch to other mode except an on-chip oscillator (Select one of 1/1, 1/2, and 1/8)
Switch the clock division ratio selection bits (bits 6 and 7 of CPUM)
Main routine
Note. After releasing reset the operation starts by starting an on-chip oscillator automatically. Do not use an on-chip oscillator at ordinary operation.
Fig. 11 Switching method of CPU mode register
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors.
Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
000016 SFR area 004016 010016 Zero page
RAM RAM area
RAM capacity (bytes) address XXXX16
XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area
(128 bytes)
256 384
013F16 01BF16
ZZZZ16
ROM ROM area
ROM capacity (bytes) address YYYY16 address ZZZZ16
FF0016
8192 16384
E00016 C00016
E08016 C08016
FFEC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area
Special page
Fig. 12 Memory map diagram
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516
USB interrupt control register (USBICON) USB transmit data byte number set register 0 (EP0BYTE) USB transmit data byte number set register 1 (EP1BYTE) USBPID control register 0 (EP0PID) USBPID control register 1 (EP1PID) USB address register (USBA) USB sequence bit initialization register (INISQ1) USB control register (USBCON) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS)
Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2)
A/D control register (ADCON) A/D conversion register (low-order) (ADL) A/D conversion register (high-order) (ADH)
Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit/Receive buffer register (TB/RB)
USB status register (USBSTS)/UART status register (UARTSTS)
003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1)
Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) USB data toggle synchronization register ( TRSYNC) USB interrupt source discrimination register 1 (USBIR1) USB interrupt source discrimination register 2 (USBIR2)
Interrupt control register 1 (ICON1)
Fig. 13 Memory map of special function register (SFR)
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
I/O Ports
[Direction registers] PiD The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds to individual pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating.
[Pull-up control] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. [Port P1P3 control] P1P3C By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36 and P37 by program. Then, as for the 36-pin version, set "1" to each bit 6 of the port P3 direction register and port P3 register. As for the 32-pin version, set "1" to respective bits 5, 6, 7 of the port P3 direction register and port P3 register.
b7
b0
Pull-up control register (PULL: address 0016 16)
P00 pull-up control bit P01 pull-up control bit P02, P03 pull-up control bit P04 - P07 pull-up control bit P30 - P33 pull-up control bit P34 pull-up control bit P35, P36 pull-up control bit P37 pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
0: Pull-up off 1: Pull-up on Initial value: FF16
Fig. 14 Structure of pull-up control register
b7
b0
Port P1P3 control register (P1P3C: address 0017 16) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit 0 : CMOS level 1 : TTL level P10,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used
Fig. 15 Structure of port P1P3 control register
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Table 5 I/O port function table Name Pin Input/output P00-P07 P10/RxD/DP11/TxD/D+ P12/SCLK P13/SDATA P14/CNTR0 P15, P16 P20/AN0- P27/AN7 P30-P35 P36/INT1 P37/INT0 P40, P41 Port P4 Port P2 Port P3 Port P0 Port P1 I/O individual bits
I/O format *CMOS compatible input level *CMOS 3-state output *USB input/output level when selecting USB function *CMOS compatible input level *CMOS 3-state output (Note)
Non-port function Key input interrupt Serial I/O1 function input/output Serial I/O2 function input/output
Related SFRs Diagram No. Pull-up control register (1) Serial I/O1 control register Serial I/O2 control register (2) (3) (4) (5) (6) (10) (7) (8)
Timer X function input/output Timer X mode register A/D conversion input A/D control register
External interrupt input
Interrupt edge selection register
(9) (10)
Note: Port P10, P12, P13, P36, P37 is CMOS/TTL input level.
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
(1) Port P0
Pull-up control Direction register
(2) Port P10
Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Receive enable bit Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Direction register Data bus Port latch
Data bus
Port latch
P10,P12,P13 input level selection bit To key input interrupt generating circuit
Serial I/O1 input
*
(3) Port P11
P-channel output disable bit Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6) Transmit enable bit Direction register Data bus Port latch + D- output USB output enable (internal signal) D- input
USB differential input
Serial I/O1 output D+ input D+ output USB output enable (internal signal)
(4) Port P12
SCLK pin selection bit Direction register
(5) Port P13
Signals during the SDATA output action SDATA pin selection bit Direction register
Data bus
Port latch Data bus P10,P12,P13 input level selection bit Serial I/O2 clock output Serial I/O2 clock input Serial I/O2 clock output Port latch
SDATA pin selection bit
P10,P12,P13 input level selection bit
*
Serial I/O2 clock input
*
P10, * : WhenP12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register. the TTL level is selected, there is no hysteresis characteristics.
Fig. 16 Block diagram of ports (1)
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
(6) Ports P14
(7) Ports P20-P27
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Pulse output mode Timer output CNTR0 interrupt input
A/D converter input Analog input pin selection bit
(8) Ports P30-P35
Pull-up control
Direction register
(9) Ports P36, P37
Pull-up control
Direction register
Data bus Data bus Port latch
Port latch
P37/INT0 input level selection bit
INT interrupt input
*
(10) Ports P15, P16, P40, P41
Direction register
Data bus
Port latch
* : P10, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 17 Block diagram of ports (2)
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by 14 different sources : 4 external sources, 9 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. It becomes usable by switching CNTR0 and A/D interrupt sources with bit 7 of the interrupt edge selection register, timer 2 and serial I/ O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt sources with bit 5, and serial I/O transmit and INT1 interrupt sources with bit 4. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Table 6 Interrupt vector address and priority Interrupt source Reset (Note 2) UART receive USB IN token UART transmit
USB SETUP/OUT token Reset/Suspend/Resume
Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. Notes on use When the active edge of an external interrupt (INT0, INT1, CNTR0) is set, the interrupt request bit may be set. Therefore, please take following sequence: 1. Disable the external interrupt which is selected. 2. Change the active edge in interrupt edge selection register. (in case of CNTR0: Timer X mode register) 3. Clear the set interrupt request bit to "0". 4. Enable the external interrupt which is selected.
Vector addresses (Note 1) Priority 1 2 3
High-order Low-order
Interrupt request generating conditions At reset input At completion of UART data receive At detection of IN token At completion of UART transmit shift or when transmit buffer is empty At detection of SETUP/OUT token or At detection of Reset/ Suspend/ Resume At detection of either rising or falling edge of INT1 input
Remarks Non-maskable Valid in UART mode Valid in USB mode Valid in UART mode Valid in USB mode External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) STP release timer underflow
FFFD16 FFFB16 FFF916
FFFC16 FFFA16 FFF816
INT1 INT0 Timer X Key-on wake-up Timer 1 Timer 2 Serial I/O2 CNTR0 A/D conversion BRK instruction 8 FFEF16 FFEE16 6 7 FFF316 FFF116 FFF216 FFF016 4 5 FFF716 FFF516 FFF616 FFF416
At detection of either rising or falling edge of INT0 input At timer X underflow At falling of conjunction of input logical level for port P0 (at input) At timer 1 underflow At timer 2 underflow At completion of transmit/receive shift At detection of either rising or falling edge of CNTR0 input At completion of A/D conversion
External interrupt (active edge selectable) Non-maskable software interrupt
At BRK instruction execution 9 FFED16 FFEC16 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Interrupt request
Fig. 18 Interrupt control
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns "0" when read) Serial I/O1 or INT1 interrupt selection bit 0 : Serial I/O1 1 : INT1 Timer X or key-on wake up interrupt selection bit 0 : Timer X 1 : Key-on wake up Timer 2 or serial I/O2 interrupt selection bit 0 : Timer 2 1 : Serial I/O2 CNTR0 or AD converter interrupt selection bit 0 : CNTR0 1 : AD converter
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) UART receive/USB IN token interrupt request bit UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT1 interrupt request bit INT0 interrupt request bit Timer X or key-on wake up interrupt request bit Timer 1 interrupt request bit Timer 2 or serial I/O2 interrupt request bit CNTR0 or AD converter interrupt request bit 0 : No interrupt request issued Not used (returns "0" when read) 1 : Interrupt request issued
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) UART receive/USB IN token interrupt enable bit UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT1 interrupt enable bit INT0 interrupt enable bit Timer X or key-on wake up interrupt enable bit Timer 1 interrupt enable bit Timer 2 or serial I/O2 interrupt enable bit CNTR0 or AD converter interrupt enable bit Not used (returns "0" when read) 0 : Interrupts disabled (Do not write "1" to this bit) 1 : Interrupts enabled
Fig. 19 Structure of Interrupt-related registers
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying "L" level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 20, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports.
Port PXx "L" level output PULL register bit 3 = "0" * P07 output ** Port P07 latch
Falling edge detection
Port P07 Direction register = "1" Key input interrupt request
PULL register bit 3 = "0" * P06 output ** Port P06 latch
Port P06 Direction register = "1"
Falling edge detection
PULL register bit 3 = "0" * P05 output ** Port P05 latch
Port P05 Direction register = "1"
Falling edge detection
PULL register bit 3 = "0" * P04 output ** Port P04 latch
Port P04 Direction register = "1"
Falling edge detection
PULL register bit 2 = "1" * P03 input ** Port P03 latch
Port P03 Direction register = "0"
Falling edge detection
Port P0 Input read circuit
PULL register bit 2 = "1" * P02 input ** Port P02 latch
Port P02 Direction register = "0"
Falling edge detection
PULL register bit 1 = "1" * P01 input ** Port P01 latch
Port P01 Direction register = "0"
Falling edge detection
PULL register bit 0 = "1" * P00 input ** Port P00 latch
Port P00 Direction register = "0"
Falling edge detection
* P-channel transistor for pull-up ** CMOS output buffer
Fig. 20 Connection example when using key input interrupt and port P0 block diagram
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Timers
The 7534 Group has 3 timers: timer X, timer 1 and timer 2. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches "0", an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to "1".
b7 b0
Timer X mode register (TM : Address 002B16) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop Not used (return "0" when read)
qTimer 1, Timer 2
Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always count the prescaler output and periodically sets the interrupt request bit.
qTimer X
Timer X can be selected in one of 4 operating modes by setting the timer X mode register. * Timer Mode The timer counts the signal selected by the timer X count source selection bit. * Pulse Output Mode The timer counts the signal selected by the timer X count source selection bit, and outputs a signal whose polarity is inverted each time the timer value reaches "0", from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the output of the CNTR0 pin is started with an "H" output. At "1", this output is started with an "L" output. When using a timer in this mode, set the port P14 direction register to output mode. * Event Counter Mode The operation in the event counter mode is the same as that in the timer mode except that the timer counts the input signal from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the timer counts the rising edge of the CNTR0 pin. When this bit is "1", the timer counts the falling edge of the CNTR0 pin. * Pulse Width Measurement Mode When the CNTR0 active edge switch bit is "0", the timer counts the signal selected by the timer X count source selection bit while the CNTR0 pin is "H". When this bit is "1", the timer counts the signal while the CNTR0 pin is "L". In any mode, the timer count can be stopped by setting the timer X count stop bit to "1". Each time the timer overflows, the interrupt request bit is set.
Fig. 21 Structure of timer X mode register
b7
b0
Timer count source set register (TCSS : Address 002E16) Timer X count source selection bit (Note) 0 : f(XIN)/16 1 : f(XIN)/2 Not used (return "0" when read) Note : To switch the timer X count source selection bit , stop the timer X count operation.
Fig. 22 Timer count source set register
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Data bus
f(XIN)/16 f(XIN)/2 Timer X count source selection bit CNTR0 active edge switch bit "0"
Prescaler X latch (8) Pulse width measurement mode Timer mode pulse output mode Prescaler X (8) Event counter mode Timer X count stop bit
Timer X latch (8)
Timer X (8)
To timer X interrupt request bit To CNTR0 interrupt request bit
P14/CNTR0
"1" CNTR0 active edge switch bit "1" Q Q "0" Port P14 latch Port P14 direction register Pulse output mode Toggle flip-flop R T Timer X latch write Pulse output mode
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
f(XIN)/16
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit To timer 1 interrupt request bit
Fig. 23 Block diagram of timer X, timer 1 and timer 2
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Serial Interface qSerial I/O1
* Asynchronous serial I/O (UART) mode Serial I/O1 can be used as an asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation when serial I/O1 is in operation. Eight serial data transfer formats can be selected, and the transfer formats to be used by a transmitter and a receiver must be identical. Each of the transmit and receive shift registers has a buffer register
Data bus Address (001816) OE Receive Buffer Register
(the same address on memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the respective buffer registers. These buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession. By selecting "1" for continuous transmit valid bit (bit 2 of SIO1CON), continuous transmission of the same data is made possible. This can be used as a simplified PWM.
Serial I/O1 control register Address (001A16) Receive buffer full flag (RBF) Receive interrupt request (RI)
Character length selection bit P10/RXD ST Detector 7-bit 8-bit PE FE SP Detector Receive Shift Register
1/16 UART Control Register Address (001B16) Clock Control Circuit
BRG count source selection bit XIN 1/4
Division ratio 1/(n+1) Baud Rate Generator Address (001C16) ST/SP/PA Generator 1/16 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI)
P11/TXD Character length selection bit
Transmit Shift Register
Transmit Buffer Register Continuous transmit valid bit Data bus Address (001816)
Transmit buffer empty flag (TBE) Serial I/O1 status register Address (001916)
Fig. 24 Block diagram of UART serial I/O1
Transmit/Receive Clock Transmit Buffer Register Write Signal TBE=0 TSC=0 TBE=1 Serial Output TXD
ST D0
TBE=0 TBE=1
D1 SP ST D0 D1
TSC=1*
SP
Receive Buffer Register Read Signal
1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit
* Generated at second bit in 2-stop -bit mode
RBF=0 RBF=1 Serial Input RXD
ST D0 D1 SP ST D0 D1
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer at TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Fig. 25 Operation of UART serial I/O1 function
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
[Serial I/O1 control register] SIO1CON The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART control register] UARTCON The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P11/TxD pin. [UART status register] UARTSTS The read-only UART status register consists of seven flags (bits 0 to 6) which indicate the operating status of the UART function and various errors. This register functions as the UART status register (UARTSTS) when selecting the UART. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the UART status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 mode selection bits MOD1 and MOD0 (bit 7 and 6 of the Serial I/O1 control register ) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "8116" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the continuous transmit valid bit (bit 2) becomes "1". [Transmit/Receive buffer register] TB/RB The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7-bit, the MSB of data stored in the receive buffer is "0".
[Baud Rate Generator] BRG The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
Transmit/Receive Clock Transmit Buffer Register Write Signal TBE=0 TSC=0 TBE=1 Serial Output TXD
ST D0 D1 SP ST D0 D1 SP ST
1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit
Notes 1 : When the serial I/O1 mode selection bits (b7, b6) is "10", the transmit enable bit is "1", and continuous transmit valid bit is "1", writing on the transmit buffer initiates continuous transmission of the same data. 2 : Select 0 for continuous transmit valid bit to stop continuous transmission. The TXD pin will stop at high level after completing transmission of 1 byte. 3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after completing transmission of 1 byte.
Fig. 26 Continuous transmission operation of UART serial I/O
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
* Universal serial bus (USB) mode By setting bits 7 and 6 of the serial I/O1 control register (address 001A16) to "11", the USB mode is selected. This mode conforms to Low-Speed USB2.0 specification. In this mode serial I/O1 interrupt have 6 sources; USB in and out token receive, set-up token receive, USB reset, suspend, and resume. The USB status/UART status
register functions as the USB status register (USBSTS).There is the USBVREFOUT pin for the USB reference voltage output, and a Dline with 1.5 k external resistor can be pull up. USB mode block and USB transceiver block show in figures 27 and 28.
Data bus 1.5 MHz XIN 6 MHz Address 001816
Receive buffer register
RxRDY
Digital PLL
NRZI, bit stuffing decoder
Receive shift register
BSTFE
SYNC decoder
EOP Differential input and Single end input Bus state detection PID decoder Reset interrupt request
PIDE RxPID OPID
P10/DP11/D+
Suspend interrupt request USB transceiver Resume interrupt request
Address comparative unit
USBA
Token interrupt request
End pointer decoder Output data and I/O control CRC check
RxEP
CRCE
NRZI, bit stuffing encoder USB transmit unit EOP generating unit CRC encoder
Transmit shift register SYNC, PID generating unit Transmit buffer register
Address 001816 Data bus TxRDY EP0BYTE EP1BYTE EP0PID EP1PID
Fig. 27 USB mode block diagram
Serial I/O1 control register
MOD0 MOD1 USB control register
UVOE
(initial value "0")
Output enable signal
USB reference power source voltage
Voltage input
Output amplifier
USBVREFOUT
Internal D- output signal Internal D+ output signal Suspend
D+/Doutput amplifier
DD+
Signal for function stop
OE Output enable signal (internal signal) Differential input Single end input Single end input
+
Fig. 28 USB transceiver block diagram
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
b7
b0
Transmit buffer register (TB: address 001816) After setting data to address 001816, a content of the transmit buffer register transfers to the transmit shift register automatically.
CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b7 b0
Receive buffer register (RB: address 001816) By reading data from address 001816, a content of the receive buffer register can be read out.
CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear
b7
b0
USB status register (USBSTS: address 001916) Transmit buffer empty flag 0: Buffer full 1: Buffer empty EOP detection flag 0: Not detected 1: Detect False EOP error flag 0: No error 1: False EOP error CRC error flag 0: No error 1: CRC error PID error flag 0: No error 1: PID error Bit stuffing error flag 0: No error 1: Bit stuffing error Summing error flag 0: No error 1: Summing error Receive buffer full flag 0: Buffer empty 1: Buffer full
CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear
CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set
Fig. 29 Structure of serial I/O1-related registers (1)
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
b7
b0
USB data toggle synchronization register (TRSYNC: address 001D16) Not used (return "1" when read) Sequence bit toggle flag 0: No toggle 1: Sequence toggle
b7 b0 CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set
USB interrupt source discrimination register 1 (USBIR1: address 001E16) Not used (return "1" when read) Endpoint determination flag 0: Endpoint 0 interrupt 1: Endpoint 1 interrupt
b7 b0 CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear
USB interrupt source discrimination register 2 (USBIR2: address 001F16) Not used (return "1" when read) Suspend request flag 0: No request 1: Suspend request USB reset request flag 0: No request 1: Reset request Not used (return "1" when read) Token PID determination flag 0: SETUP interrupt 1: OUT interrupt Token interrupt flag 0: No request 1: Token request
b7 b0 CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear
CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear
USB interrupt control register (USBICON: address 002016) Not used (return "1" when read) Endpoint 1 enable 0: Endpoint 1 invalid 1: Endpoint 1 valid USB reset interrupt enable 0: USB reset invalid 1: USB reset valid Resume interrupt enable 0: Resume invalid 1: Resume valid Token interrupt enable 0: Token invalid 1: Token valid USB enable flag 0: USB invalid 1: USB valid
Fig. 30 Structure of serial I/O1-related registers (2)
CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
b7
b0
USB transmit data byte number set register 0 (EP0BYTE: address 002116) Set a number of data byte for transmitting with endpoint 0.
CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
Not used (return "0" when read)
b7 b0
USB transmit data byte number set register 1 (EP1BYTE: address 002216) Set a number of data byte for transmitting with endpoint 1.
CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
Not used (return "0" when read)
b7 b0
USB PID control register 0 (EP0PID: address 002316) Not used (return "1" when read) Endpoint 0 enable flag 0: Endpoint 0 invalid 1: Endpoint 0 valid Endpoint 0 PID selection flag 1xxx: IN token interrupt of DATA0/1 is valid 01xx: STALL handshake is valid for IN token 00xx: NAK handshake is valid for IN token xxx1: STALL handshake is valid for OUT token (Note) xx10: ACK handshake is valid for OUT token xx00: NAK handshake is valid for OUT token x: any data
CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b4, b5, b6 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b7 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Clear
Note: In the status stage of the control read transfer, when PID of data packet = DATA0 (incorrect PID), this bit is set forcibly by hardware and STALL handshake is valid.
b7 b0
USB PID control register 1 (EP1PID: address 002416) Not used (return "1" when read) Endpoint 1 PID selection flag 1x: IN token interrupt of DATA0/1 is valid 01: STALL handshake is valid for IN token 00: NAK handshake is valid for IN token x: any data
b7 b0 b6 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used b7 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Clear
USB address register (USBA: address 002516) Set an address allocated by the USB host.
CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
Not used (returns "1" when read)
Fig. 31 Structure of serial I/O1-related registers (3)
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
b7
b0
USB sequence bit initialization register (INISQ1: address 002616) A sequence bit of endpoint 1 is initialized.
CPU read: Disabled CPU write: Dummy Hardware read: Not used Hardware write: Not used
b7
b0
USB control register (USBCON: address 002716) Not used (return "1" when read) USBVREFOUT output valid flag 0: Output off 1: Output on Remote wake up request flag 0: No request 1: Remote wake up request
CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used CPU read: Disabled CPU write: Set Hardware read: Used Hardware write: Clear
b7
b0
UART status register (UARTSTS: address 001916) Transmit buffer empty flag 0: Buffer full 1: Buffer empty Receive buffer full flag 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag 0: No error 1: Overrun error Parity error flag 0: No error 1: Parity error Framing error flag 0: No error 1: Framing error Summing error flag 0: No error 1: Summing error Not used (returns "1" when read)
CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear
CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set
b7
b0
Baud rate generator (BRG: address 001C16) This register is valid only when selecting the UART mode. A baud rate value is set.
CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
Fig. 32 Structure of serial I/O1-related registers (4)
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
b7
b0
UART control register (UARTCON: address 001B16) Character length selection bit 0: 8 bits 1: 7 bits Parity enable bit 0: Parity checking disabled 1: Parity checking enabled Parity selection bit 0: Even parity 1: Odd parity Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits P-channel output disable bit 0: CMOS output 1: N-channel open-drain output Not used (returns "1" when read)
CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
b7
b0
Serial I/O1 control register (SIO1CON: address 001A16) BRG count source selection bit 0: f(XIN) 1: f(XIN)/4 Not used (returns "1" when read) Continuous transmit valid bit 0: Continuous transmit invalid 1: Continuous transmit valid Transmit interrupt source selection bit 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit 0: Transmit disabled 1: Transmit enabled Receive enable bit 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bits 00: I/O port 01: Not available 10: UART mode 11: USB mode
Fig. 33 Structure of serial I/O1-related registers (5)
CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Note on using USB mode Handling of SE0 signal in program (at receiving) 7534 group has the border line to detect as USB RESET or EOP (End of Packet) on the width of SE0 (Single Ended 0). A response apposite to a state of the device is expected. The name of the following short words which is used in table 5 shows as follow. *TKNE: Token interrupt enable (bit 6 of address 2016) *RSME: Resume interrupt enable (bit 5 of address 2016) *RSTE: USB reset interrupt enable (bit 4 of address 2016) *Spec: A response of the device requested by Low-Speed USB2.0 specification *SIE: Hardware operation in 7534 group *F/W: Recommendation process in the program *FEOPE: False EOP error flag (bit 2 of address 1916) *RxPID: Token interrupt flag (bit 7 of address 1F16) Table 7 Relation of the width of SE0 and the state of the device State of device Idle state Width of SE0 TKNE = X RSME = 0 RSTE =1 Spec 0 s 0.5 s F/W Spec 0.5 s 2.5 s F/W Spec SIE 2.5 s 2.67 s F/W Keep alive or Reset may determine as keep alive and Reset interrupt Keep alive in case of no interrupt request Reset processing in case of interrupt request Reset Reset interrupt request Reset processing SIE Not acknowledge Keep alive Initialize suspend timer count value Not acknowledge Ignore Keep counting suspend timer SIE Ignore Not detected as EOP(in case of no detection EOP, SIE returns idle state as time out. FEOPE flag is set.) Not acknowledge EOP Token interrupt request Token interrupt processing execute EOP or Reset may determine as EOP and Reset interrupt RxPID = 1> Token interrupt processing RxPID = 0> Reset interrupt processing Reset Reset interrupt request Reset processing End of Token in transaction TKNE = 1 RSME = 0 RSTE =1 End of data or handshake in transaction TKNE = 0 RSME = 0 RSTE = 0 or 1 Ignore Not detected as EOP(in case of no detection EOP, SIE returns idle state as timeup. FEOPE flag is set.) Wait for the next EOP flag EOP Set EOP flag After checking the set of EOP flag, go to the next processing EOP or Reset may determine as EOP and Reset interrupt Continue the processing in case of no interrupt request Reset processing in case of interrupt request Reset Reset interrupt request Reset processing F/W Reset interrupt processing Resume interrupt processing Suspend state TKNE = 0 RSME = 1 RSTE = 0
Spec
Reset or resume
SIE
Reset interrupt request
Spec 2.67 s SIE F/W
* Function of USBPID control register 0 (address 002316) Bit 4 (STALL handshake control for OUT token) of this register is forcibly set by SIE under the special condition shown below. Set condition; when PID of data packet = DATA0 (incorrect PID) in the status stage of the control read transfer. * SYNC field at reception Normally, the SYNC field consists of "KJKJKJKK" (8 bits). However, as for SIE of the 7534 Group, when the low-order 6 bits are "KJKJKK", it is determined as SYNC.
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
qSerial I/O2
The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control various serial I/O functions. * For receiving, set "0" to bit 3. * When receiving, bit 7 is cleared by writing dummy data to serial I/ O2 register after shift is completed. * Bit 7 is set earlier a half cycle of shift clock than completion of shift operation. Accordingly, when checking shift completion by using this bit, the setting is as follows: (1) check that this bit is set to "1", (2) wait a half cycle of shift clock, (3) read/write to serial I/O2 register.
b7
b0
Serial I/O2 control register (SIO2CON: address 003016) Internal synchronous clock selection bits 000 : f(XIN)/8 001 : f(XIN)/16 010 : f(XIN)/32 011 : f(XIN)/64 110 : f(XIN)/128 111 : f(XIN)/256 SDATA pin selection bit (Note) 0 : I/O port/SDATA input 1 : SDATA output Not used (returns "0" when read) Transfer direction selection bit 0 : LSB first 1 : MSB first SCLK pin selection bit 0 : External clock (SCLK is an input) 1 : Internal clock (SCLK is an output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed
Note : When using it as an SDATA input, set the port P13 direction register to "0".
Fig. 34 Structure of serial I/O2 control registers
Data bus
1/8 1/16 Divider 1/32 1/64 1/128 1/256
XIN
SCLK pin
selection bit
"1" "0"
Internal synchronous clock selection bits
SCLK
SCLK pin selection bit
"0"
P12/SCLK
"1"
P12 latch Serial I/O counter 2 (3) Serial I/O2 interrupt request
SDATA pin selection bit
"0"
P13/SDATA
"1"
P13 latch
SDATA pin selection bit Serial I/O shift register 2 (8)
Fig. 35 Block diagram of serial I/O2
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Serial I/O2 operation By writing to the serial I/O2 register(address 003116) the serial I/O2 counter is set to "7". After writing, the SDATA pin outputs data every time the transfer clock shifts from a high to a low level. And, as the transfer clock shifts from a low to a high, the SDATA pin reads data, and at the same time the contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. * Serial I/O2 counter is cleared to "0". * Transfer clock stops at an "H" level. * Interrupt request bit is set. * Shift completion flag is set. Also, the SDATA pin is in a high impedance state after the data transfer is complete. Refer to Figure 36. When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the SDATA pin is not in a high impedance state on the completion of data transfer.
Synchronous clock
Transfer clock
Serial I/O2 register write signal (Note) SDATA at serial I/O2 output transmit SDATA at serial I/O2 input receive D0 D1 D2 D3 D4 D5 D6 D7
Serial I/O2 interrupt request bit set Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA pin is set to the input mode, the SDATA pin is in a high impedance state after the data transfer is completed.
Fig. 36 Serial I/O2 timing (LSB first)
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
A/D Converter
The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/D conversion. [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during A/D conversion, and changes to "1" at completion of A/D conversion. A/D conversion is started by setting this bit to "0" except during an A/ D conversion. [Comparison voltage generator] The comparison voltage generator divides the voltage between VSS and VREF by 1024 by a resistor ladder, and outputs the divided voltages. Since the generator is disconnected from VREF pin and VSS pin, current is not flowing into the resistor ladder. [Channel Selector] The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A/D conversion.
b7
b0
A/D control register (ADCON : address 003416) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 111 : P27/AN7 Not used (returns "0" when read) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read)
Fig. 37 Structure of A/D control register
Read 8-bit (Read out only address 003516) b7 (Address 003516) b9 b8 b7 b6 b5 b4 b3
b0 b2
Read 10-bit (read out in order address 003616, 003516) b7 (Address 003616) b7 (Address 003516) b7 b6 b5 b4 b3 b2 b1 b9
b0 b8 b0 b0
High-order 6-bit of address 003616 returns "0" when read.
Fig. 38 Structure of A/D conversion register
Data bus
b7 A/D control register (Address 003416) 3 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 A/D control circuit
Channel selector
b0
A/D interrupt request
A/D conversion register (high-order)
Comparator
(Address 003616) (Address 003516)
A/D conversion register (low-order) 10 Resistor ladder
VREF Fig. 39 Block diagram of A/D converter
VSS
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Watchdog Timer
The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 003916), the watchdog timer H is set to "FF16" and the watchdog timer L is set to "FF16".
Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is "0", the count source becomes a watchdog timer L underflow signal. The detection time is 174.763 ms at f(XIN)=6 MHz. When this bit is "1", the count source becomes f(XIN)/16. In this case, the detection time is 683 s at f(XIN)=6 MHz. This bit is cleared to "0" after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address 003916). When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to "1", it cannot be changed to "0" by program. This bit is cleared to "0" after reset.
Data bus Write "FF16" to the watchdog timer control register Watchdog timer L (8) 1/16 Write "FF16" to the watchdog timer control register
"0" "1" Watchdog timer H (8)
XIN
Watchdog timer H count source selection bit STP Instruction Disable Bit STP Instruction Reset circuit Internal reset
RESET
Fig. 40 Block diagram of watchdog timer
b7
b0
Watchdog timer control register(address 0039 16) WDTCON Watchdog timer H (read-only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16
Fig. 41 Structure of watchdog timer control register
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Reset Circuit
The microcomputer is put into a reset status by holding the RESET pin at the "L" level for 15 s or more when the power source voltage is 4.1 to 5.5 V and XIN is in stable oscillation. After that, this reset status is released by returning the RESET pin to the "H" level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address. Note that the reset input voltage should be 0.82 V or less when the power source voltage passes 4.1 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2 VCC
Note : Reset release voltage Vcc = 4.1 V
RESET
VCC Power source voltage detection circuit
Fig. 42 Example of reset circuit
Clock from on-chip oscillator RESET RESETOUT SYNC Address Data
? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD
ADH,ADL
ADH
Reset address from the vector table
8-13 clock cycles
Notes 1 : An on-chip oscillator applies about 250 kHz frequency as clock f at average of Vcc = 5 V. 2 : The mark "?" means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET
Fig. 43 Timing diagram at reset
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Port P4 direction register (6) Pull-up control register (7) USB/UART status register (8) Serial I/O1 control register (9) UART control register (10) USB data toggle synchronization register (11) USB interrupt source discrimination register 1 (12) USB interrupt source discrimination register 2 (13) USB interrupt control register (14) USB transmit data byte number set register 0 (15) USB transmit data byte number set register 1 (16) USBPID control register 0 (17) USBPID control register 1 (18) USB address register (19) USB sequence bit initialization register (20) USB control register (21) Prescaler 12 (22) Timer 1 (23) Timer 2 (24) Timer X mode register (25) Prescaler X (26) Timer X (27) Timer count source set register (28) Serial I/O2 control register (29) A/D control register (30) MISRG (31) Watchdog timer control register (32) Interrupt edge selection register (33) CPU mode register (34) Interrupt request register 1 (35) Interrupt control register 1 (36) Processor status register (37) Program counter 000116 000316 000516 000716 000916 001616 001916 001A16 001B16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 003016 003416 003816 003916 003A16 003B16 003C16 003E16 (PS) (PCH) (PCL)
X 1 0 0 0 1 1 0 1 0 0 0 0 1 X X
Register contents
0016 0 0 0 0 0 0 0
0016 0016 X X X X X 0 0
FF16 0 0 0 0 0 0 1
0216 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1
0016 0016 0 0 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1
FF16 0116 0016 0016 FF16 FF16 0016 0016 1016 0016 0 1 1 1 1 1 1
0016 0 0 0 0 0 0 0
0016 0016 X X X X 1 X X
Contents of address FFFD16 Contents of address FFFC16
Note X : Undefined
Fig. 44 Internal status of microcomputer at reset
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.)
XIN
XOUT Rd (Note)
qOscillation control
* Stop mode When the STP instruction is executed, the internal clock stops at an "H" level and the XIN oscillator stops. At this time, timer 1 is set to "0116" and prescaler 12 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 12 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 12. When an external interrupt is accepted, oscillation is restarted but the internal clock remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. ______ So apply an "L" level to the RESET pin while oscillation becomes stable. * Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. When the STP status is released, prescaler 12 and timer 1 will start counting clock which is XIN divided by 16, so set the timer 1 interrupt enable bit to "0" before the STP instruction is executed. Note For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 12 after fully appreciating the oscillation stabilization time of the oscillator to be used. * Clock mode Operation is started by an on-chip oscillator after releasing reset. A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the CPU mode register after releasing it.
CIN
COUT
Note : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction.
Fig. 45 External circuit of ceramic resonator
XIN
XOUT Open
External oscillation circuit VCC VSS
Fig. 46 External clock input circuit
b7
b0
MISRG(Address 003816) Oscillation stabilization time set bit after release of the STP instruction 0: Set "0116" in timer1, and "FF16" in prescaler 12 automatically 1: Not set automatically Reserved bits (return "0" when read) (Do not write "1" to these bits) Not used (return "0" when read)
Fig. 47 Structure of MISRG
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION
XIN
(Note 2)
XOUT Rf Rd
Clock division ratio selection bit Middle-speed, High-speed, double -speed mode
1/2
On-chip oscillator mode
1/4
1/2
Prescaler 12
Timer 1
Clock division ratio selection bit Middle-speed mode High-speed mode Double-speed mode On-chip oscillator (Note 1)
Timing (Internal clock)
1/8
On-chip oscillator mode
QS R STP instruction WIT instruction
S R
Q
Q
S R STP instruction
Reset Interrupt disable flag l Interrupt request
Note 1: On-chip oscillator is used only for starting. 2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Fig. 48 Block diagram of system clock generating circuit (for ceramic resonator)
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HARDWARE 7534 Group NOTES ON PROGRAMMING/NOTES ON USE
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations.
Watchdog Timer
The internal reset may not be generated correctly in the middle-speed mode, depending on the underflow timing of the watchdog timer. When using the watchdog timer, operate the MCU in any mode other than the middle-speed mode (i.e., high-speed, low-speed or doublespeed mode).
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode.
Interrupts
The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction.
Note on stack page
When 1 page is used as stack area by the stack page selection bit, the area which can be used as stack depends on RAM size. Especially, be careful that the RAM area varies in Mask ROM version, One Time PROM version and Emulator MCU.
Decimal Calculations
* For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid.
NOTES ON USE Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic or electrolytic capacitor of 1.0 F is recommended.
Timers
* When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When a count source of timer X is switched, stop a count of timer X.
Ports
* The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. * As for the 36-pin version, set "1" to each bit 6 of the port P3 direction register and the port P3 register. * As for the 32-pin version, set "1" to respective bits 5, 6, 7 of the port P3 direction register and port P3 register.
Handling of USBVREFOUT Pin
In order to prevent the instability of the USBVREFOUT output due to external noise, connect a capacitor as bypass capacitor between USBVREFOUT pin and GND pin (VSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor, a ceramic or electrolytic capacitor of 0.22 F is recommended.
USB Communication
* In applications requiring high-reliability, we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due to external causes such as noise. * When USB suspend mode with TTL level on P10, P12, P13 input level selection bit (bit 3 of address 1716) set to "1", suspend current as ICC might be greater than 300 A as a spec. [Countermeasure] There are two countermeasures by software to avoid it as follows. (1) Change from TTL input level to CMOS input level for P10, P12, P13 port input. (2) Change from TTL input level to CMOS input level before STP instruction in suspend routine; then after RESUME or Remote wake up interrupt, return to TTL input level from CMOS input level. That is shown in Figure 49.
A/D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500kHz or more during A/D conversion. Do not execute the STP instruction during A/D conversion.
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HARDWARE 7534 Group DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
Note on A/D Converter
SUSPEND Routine
Configuration to CMOS input level for P10, P12, P13 input level.
P1P3C xxxxx0xx2
Configuration to CMOS input level for P10, P12, P13 input level.
STP
Method to stabilize A/D Converter is described below. (a) A/D conversion accuracy could be affected for Bus Powered*1 USB devices, while the communicating. Figure 50 shows the method to stabilize A/D conversion accuracy, inserting a capacitor between Vref and VSS. *1: Power supplied by USB VCC BUS.
RESUME Routine
AN0 to AN7
Configuration to TTL input level for P10, P12, P13 input level.
D-
P1P3C xxxxx1xx2
Configuration to TTL input level for P10, P12, P13 input level.
1.5 k Vcc USBVREFOUT 0.22 F 7534 Group CNVss
Remote wake up Routine
0.01 to 1 F
1 F
Configuration to TTL input level for P10, P12, P13 input level.
P1P3C xxxxx1xx2
Configuration to TTL input level for P10, P12, P13 input level.
Vref 1 to 10 k Vss
Fig. 49 Countermeasure (2) by software
0.1 to 1 F : Recommends for A/D accuracy
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor. Fig. 50 Method to stabilize A/D conversion accuracy (b) It is recommended for A/D accuracy to avoid converting while USB communication, and use average value of several converted values.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) * For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com).
Electric Characteristic Differences Among Mask ROM and One TIme PROM Version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
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HARDWARE 7534 Group
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 8 Special programming adapter Package Name of Programming Adapter PLQP0032GB-A PRSP0036GA-A PRDP0042BA-A PCA7435GPG03 PCA7435FP, PCA7435FPG02 PCA7435SP, PCA7435SPG02
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 51 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150 C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 51 Programming and testing of One Time PROM version
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt 7534 group permits interrupts on the 14 sources for 42-pin version, 13 sources for 36-pin version and 12 sources for 32-pin version. It is vector interrupts with a fixed priority system. Accordingly,
when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to "Table 9."
Table 9 Interrupt sources, vector addresses and interrupt priority
Interrupt source Reset (Note 2) UART receive USB IN token UART transmit
USB SETUP/OUT token Reset/Suspend/Resume
Vector addresses (Note 1) Priority 1 2 3
High-order Low-order
Interrupt request generating conditions At reset input At completion of UART data receive At detection of IN token At completion of UART transmit shift or when transmit buffer is empty At detection of SETUP/OUT token or At detection of Reset/ Suspend/ Resume At detection of either rising or falling edge of INT1 input
Remarks Non-maskable Valid in UART mode Valid in USB mode Valid in UART mode Valid in USB mode External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) STP release timer underflow
FFFD16 FFFB16 FFF916
FFFC16 FFFA16 FFF816
INT1 (Note 3) INT0 (Note 4) Timer X Key-on wake-up Timer 1 Timer 2 Serial I/O2 CNTR0 A/D conversion BRK instruction 9 FFED16 FFEC16 8 FFEF16 FFEE16 6 7 FFF316 FFF116 FFF216 FFF016 4 5 FFF716 FFF516 FFF616 FFF416
At detection of either rising or falling edge of INT0 input At timer X underflow At falling of conjunction of input logical level for port P0 (at input) At timer 1 underflow At timer 2 underflow At completion of transmit/receive shift At detection of either rising or falling edge of CNTR0 input At completion of A/D conversion At BRK instruction execution
External interrupt (active edge selectable) Non-maskable software interrupt
Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: The INT1 interrupt does not exist in the 36-pin and 32-pin version. 4: The INT0 interrupt does not exist in the 32-pin version.
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the
instruction that is currently in execution. Figure 52 shows a timing chart after an interrupt occurs, and Figure 53 shows the time up to execution of the interrupt processing routine.
SYNC RD WR Address bus Data bus PC Not used
S, SPS S-1, SPS S-2, SPS
BL AL
BH
AL, AH AH
PCH PCL
PS
SYNC : CPU operation code fetch cycle BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : "0016" or "0116"
Fig. 52 Timing chart after an interrupt occurs
Generation of interrupt request
Start of interrupt processing
Main routine
Waiting time for post-processing of pipeline
Stack push and Vector fetch
Interrupt processing routine
0 to 7 cycles
2 cycles
5 cycles
7 to 14 cycles (At performing 6.0 MHz, in double-speed mode, 1.17 s to 2.34 s)
Fig. 53 Time up to execution of the interrupt processing routine
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT
A/D Converter A/D conversion is started by setting AD conversion completion bit to "0." During A/D conversion, internal operations are performed as follows. 1. After the start of A/D conversion, A/D conversion register goes to "0016." 2. The highest-order bit of A/D conversion register is set to "1," and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of A/D conversion register becomes "1." When Vref > VIN, the highest-order bit becomes "0."
By repeating the above operations up to the lowestorder bit of the A/D conversion register, an analog value converts into a digital value. A/D conversion completes at 122 clock cycles (20.34 s at f(XIN) = 6.0 MHz) after it is started, and the result of the conversion is stored into the A/D conversion register. Concurrently with the completion of A/D conversion, A/D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to "1."
Relative formula for a reference voltage VREF of A/D converter and Vref When n = 0 When n = 1 to 1023 Vref = 0 Vref = VREF n 1024 n : the value of A/D converter (decimal numeral)
Table 10 Change of A/D conversion register during A/D conversion Change of A/D conversion register At start of conversion First comparison Second comparison Third comparison * * * After completion of tenth comparison
Value of comparison voltage (Vref) 0 0 0 0 VREF 2 VREF 2 VREF 2 VREF VREF 8 0
0 1 1 1
0 0 1 2
0 0 0 1
0 0 0 0
0 0 0 0 * * *
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
4 VREF 4 * * *
A result of A/D conversion 1 2 3 4 5
6
7
8
9
10
VREF 2
VREF 4
***
VREF 1024
1-10: A result of the first to tenth comparison
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 54 shows A/D conversion equivalent circuit, and Figure 55 shows A/D conversion timing chart.
VCC
ANi (i=0 to 7: 42-pin version, 36-pin version i=0 to 5: 32-pin version)
(Note 1) R 1.5 k(Typical) SW1 (Note 2) C2 1.5 pF(Typical)
C1 12 pF(Typical)
(Note 1) Typical voltage generation circuit Switch tree, ladder resistor Chopper Amp.
VSS
VSS
Notes 1: This is a parasitic diode. 2: Only the selected analog input pin is turned on.
A/D control circuit
VSS
VREF
Fig. 54 A/D conversion equivalent circuit
XIN
Write signal for A/D control register
122 XIN cycles
AD conversion completion bit
Sampling clock
Fig. 55 A/D conversion timing chart
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT
Stop mode System enters the stop mode by executing the STP instruction. In the stop mode, the f(XIN) oscillation is stopped, and the internal clock is stopped. Accordlingly, CPU and the peripheral devices are stopped. (1) Stop mode state Table 11 shows the state at stop mode. Table 11 Stop mode state Parameter Oscillation CPU I/O port Timer Stop Stop State retained at STP instruction execution At selecting internal count source: Stop At selecting external count source: Operating (only Timer X) Stop UART A/D conversion Stop At selecting internal synchronous Serial I/O2 clock: Stop At selecting external synchronous clock: Operating Stop (suspend state)
State
Parameter Watchdog timer Stop RAM SFR CPU register State retained
State
State retained (Timer 1 and prescaler 12 excepted) State retained * Accumulator * Index register X * Index register Y * Stack pointer * Program counter * Processor status register
USB
(2) Stop mode release Stop mode is released by reset input or interrupt occurrence. The interrupt sources which can be used for return from stop mode are shown below. * * * * * * * INT0 INT1 CNTR0 Timer (Timer X) when using external clock Serial I/O2 when using external clock Key-on wakeup USB function (resume, reset)
When the above interrupt sources are used for return from stop mode, execute the STP instruction after the following are set in order to enable the using interrupts. Clear the timer 1 interrupt enable bit to "0" (ICON1, bit 4) Clear the timer 2 interrupt enable bit to "0" (ICON1, bit 5) Clear the timer 1 interrupt request bit to "0" (IREQ1, bit 4) Clear the timer 2 interrupt request bit to "0" (IREQ1, bit 5) Clear the interupt request bit of the interrupt using for return to "0" Set the interupt enable bit of the interrupt using for return to "1" Clear the interrupt disable flag (I) to "0"
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HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT
Wait mode System enters the wait mode by executing the WIT instruction. In the wait mode, the oscillation is operating, but the internal clock is stopped. Accordlingly, CPU is stopped, but the peripheral devices are operating. (1) Wait mode state Table 12 shows the state at wait mode. Table 12 Wait mode state Parameter Oscillation CPU I/O port Timer Stop Stop State at WIT instruction execution retained At selecting internal count source: Operating At selecting external count source: Operating Operating
State
Parameter Watchdog timer Operating RAM SFR CPU register State retained
State
State retained (Timer 1, timer 2 and prescaler 12 excepted) State retained * Accumulator * Index register X * Index register Y * Stack pointer * Program counter * Processor status register
UART
A/D conversion O p e r a t i n g ( C o n v e r s i o n i s continued if the WIT instruction is executed during conversion) Serial I/O2 At selecting internal synchronous clock: Operating At selecting external synchronous clock: Operating USB Operating
(2) Wait mode release Wait mode is released by reset input or interrupt occurrence. In the wait mode, since the oscillation is continued, the instruction is executed after the system is released from the wait mode. The interrupt sources which can be used for return from wait mode are shown below. * * * * * * * * * INT0 INT1 CNTR0 Timer Serial I/O2 A/D conversion Key-on wakeup USB function UART
When the above interrupt sources are used for return from wait mode, execute the WIT instruction after the following are set in order to enable the using interrupts. Clear the interupt request bit of the interrupt using for return to "0" Set the interupt enable bit of the interrupt using for return to "1" Clear the interrupt disable flag (I) to "0"
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HARDWARE 7534 Group DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP/ DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP
Table 13 Description of improved USB function for 7534 Group Parameter No. 1 Response at Control transfer 2 D+/D- transceiver circuit 7534 Group Connectable to the host which performs the Control transfer in parallel to plural device. Deal with the following Low-Speed USB2.0 specification. CL = 200 pF to 450 pF, Trise and Tfall: 75 ns to 300 ns, Tr/Tf: 80 % to 125 %, Cross over Voltage: 1.3 V to 2.0 V. Rating is Max. 300 A not including the output cur- Rating is Max. 300 A including the output current rent of USBVREFOUT. of USBVREFOUT, by low-power dissipation of D+/ D- input circuit and 3.3 V-regulator. ACK is returned once to OUT (DATA0) to be valid STALL is set automaticcally by hardware when in Status stage. OUT (DATA0) is received in Status stage. SYNC is detected only when 8-bit full code (8016) SYNC is detected only the low-order 6 bits even if is complete. the high-order 2 bits are corrupted. 7532/7536 Group Not deal with the host which performs the Control transfer in parallel to plural device. USB function can be used only at the condition of CL = 150 pF to 350 pF.
3 Power dissipation at Suspend
4 STALL in Status stage 5 6-bit decode of SYNC field
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
The 7534 Group has three package types, and each of the number of I/O ports are different. Accordingly, when the pins which have the function except a port function are eliminated, be careful that the functions are also eliminated. Table 14 Differences among 32-pin, 36-pin and 42-pin I/O port Port P1 Port P2 Port P3 Port P4 42-pin SDIP P10-P16 (7-bit structure) P20-P27 (8-bit structure) (A/D converter 8-channel) P30-P37 (8-bit structure) (INT0, INT1 available) P40, P41 (2-bit structure) 36-pin SSOP P10-P14 (5-bit structure) P20-P27 (8-bit structure) (A/D converter 8-channel) P30-P35, P37 (7-bit structure) (INT0 available) No port 32-pin LQFP P10-P14 (5-bit structure) P20-P25 (6-bit structure) (A/D converter 6-channel) P30-P34 (5-bit structure) (INT function not available) No port
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HARDWARE 7534 Group DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
Additionally, there are differences of SFR usage and functional definitions. Table 15 Differences among 32-pin, 36-pin and 42-pin (SFR) Register (Address) Port P1/Direction (0216/0316) Port P2/Direction (0416/0516) Port P3/Direction (0616/0716) Port P4/Direction (0816/0916) Pull-up control (1616) Bit 6 definition: "P35, P36 pull-up control" Bit 7 definition: "P37 pull-up control" Port P1P3 control (1716) Bit 0 definition: "P37/INT0 input level selection" Bit 1 definition: "P36/INT1 input level selection" A/DControl (3416) Interrupt edge selection (3A16) Bits 0 to 2 bits to 000 to 111" Bit 0 definition "INT0 interrupt edge selection" Bit 1 definition "INT1 interrupt edge selection" Bit 4 definition "Serial I/O1, INT1 interrupt selection" Interrupt request (3C16) Bit 1 definition INT1" Bit 2 definition "INT0" Interrupt control (3E16) Bit 1 definition INT1" Bit 2 definition "INT0" Bit 1 definition Bit 2 definition "INT0" Bit 1 definition Bit 2 not available "UART transmission, USB (except IN), "UART transmission, USB (except IN)" "UART transmission, USB (except IN)" Bit 1 definition Bit 2 definition "INT0" Bit 1 definition Bit 2 not available "UART transmission, USB (except IN), "UART transmission, USB (except IN)" "UART transmission, USB (except IN)" Bits 0 to 2 bits to 000 to 111" Bit 0 definition "INT0 interrupt edge selection" Bits 1 and 4 not available Bits 0 to 2 "Input pins selected by setting these bits to 000 to 101" Bits 0, 1 and 4 not available "Input pins selected by setting these "Input pins selected by setting these Bit 6 definition: "P35 pull-up control" Bit 7 definition: "P37 pull-up control" Bit 0 definition: "P37/INT0 input level selection" Bit 1 not available Bits 0 and 1 not available Bits 6 and 7 not available Bits 2 to 7 not available All bits not available All bits not available All bits available Bit 6 not available Bits 5 to 7 not available All bits available All bits available Bits 6 and 7 not available 42-pin SDIP Bit 7 not available 36-pin SSOP Bits 5 to 7 not available 32-pin LQFP Bits 5 to 7 not available
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HARDWARE 7534 Group DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
P11/TXD/D+ P10/RXD/DP07 P06 P05 P04 P03 P02 P01 P00 USBVREFOUT P37/INT0 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
Outline PRSP0036GA-A
Connect a bypass capacitor to a device as close as possible. For the capacitor, a ceramic capacitor or an electrolytic capacitor of 1.0 F is recommended.
Reason of is to reduce the effect by switcing noise of microcomputer to the analog circuit generating USBVREFOUT output. Use the bigger capacitor and connect to device at the shortest distance. Reason of is to prevent the instability of the USBVREFOUT output due to external noise.
Fig. 56 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP
M37534M4-XXXFP M37534E8FP
1.5k
Connect a capacitor to a device as close as possible. For the capacitor, a ceramic capacitor or an electrolytic capacitor of 0.22 F is recommended.
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HARDWARE 7534 Group DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
1.5k
Connect a capacitor to a device as close as possible. For the capacitor, a ceramic capacitor or an electrolytic capacitor of 0.22 F is recommended.
24
23
22
21
20
19
18
P07 P10/RXD/DP11/TXD/D+ P12/SCLK P13/SDATA P14/CNTR0 P20/AN0 P21/AN1
17
P06 P05 P04 P03 P02 P01 P00 USBVREFOUT
25 26 27 28 29 30 31 32
16 15 14
M37534M4-XXXGP M37534E4GP
13 12 11 10 9
P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN
3
5
6
7
Outline PLQP0032GB-A
Connect a bypass capacitor to a device as close as possible. For the capacitor, a ceramic capacitor or an electrolytic capacitor of 1.0 F is recommended.
Reason of is to reduce the effect by switcing noise of microcomputer to the analog circuit generating USBVREFOUT output. Use the bigger capacitor and connect to device at the shortest distance. Reason of is to prevent the instability of the USBVREFOUT output due to external noise.
Fig. 57 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGP, M37534E4GP
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P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC
1
2
4
8
HARDWARE 7534 Group DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
P14/CNTR0 P15 P16 P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 P40 P41 VREF RESET CNVSS Vcc XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P13/SDATA P12/SCLK P11/TXD/D+ P10/RXD/DP07 P06 P05 P04 P03 P02 P01 P00 USBVREFOUT P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
Outline PRDP0042BA-A
Connect a bypass capacitor to a device as close as possible. For the capacitor, a ceramic capacitor or an electrolytic capacitor of 1.0 F is recommended.
Reason of is to reduce the effect by switcing noise of microcomputer to the analog circuit generating USBVREFOUT output. Use the bigger capacitor and connect to device at the shortest distance. Reason of is to prevent the instability of the USBVREFOUT output due to external noise.
Fig. 58 Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSS
M37534E8SP M37534M4-XXXSP M37534RSS
1.5k
Connect a capacitor to a device as close as possible. For the capacitor, a ceramic capacitor or an electrolytic capacitor of 0.22 F is recommended.
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THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
CHAPTER 2 APPLICATION
2.1 2.2 2.3 2.4 2.5 2.6 I/O port Timer Serial I/O USB A/D converter Reset
APPLICATION 7534 Group 2.1 I/O port
2.1 I/O port
This paragraph explains the registers setting method and the notes relevant to the I/O ports. 2.1.1 Memory map
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D)
Fig. 2.1.1 Memory map of registers relevant to I/O port 2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0 to 4) [Address : 00 16, 0216, 0416, 0616, 0816]
B 0 Port Pi0 1 Port Pi1
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins
At reset
RW
? ? ? ? ? ? ? ?
q
2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7
Note: The following ports do not exist, so that the corresponding bits are not used. * 42-pin version: Ports P1 7, P42-P47 * 36-pin version: Ports P1 5-P17, P36, P40-P47 * 32-pin version: Ports P1 5-P17, P26, P27, P35-P37, P40-P47
Fig. 2.1.2 Structure of Port Pi (i = 0 to 4)
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APPLICATION 7534 Group 2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0 to 4) [Address : 01
16,
0316, 0516, 0716, 0916]
At reset
B
Name
Function
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
RW
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Note: The following ports do not exist, so that the corresponding bits are not used. * 42-pin version: Ports P1 7, P42-P47 * 36-pin version: Ports P1 5-P17, P36, P40-P47 * 32-pin version: Ports P1 5-P17, P26, P27, P35-P37, P40-P47
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 4)
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 16 16]
Name B 0 P00 pull-up control bit 1 P01 pull-up control bit 2 P02, P03 pull-up control bit 3 P04 - P07 pull-up control bit 4 P30 - P33 pull-up control bit 5 P34 pull-up control bit 6 P35, P36 pull-up control bit
(Note 2) P37 pull-up control bit 7 (Note 3)
Function
0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On
At reset
RW
1 1 1 1 1 1 1 1
Notes 1: Pins set to output are disconnected from the pull-up control. 2: * 36-pin version: P3 6 is not existed. * 32-pin version: Not used. 3: 32-pin version: Not used.
Fig. 2.1.4 Structure of Pull-up control register
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APPLICATION 7534 Group 2.1 I/O port
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0 Port P1P3 control register (P1P3C) [Address : 17
16]
B
Name
Function
0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level
At reset
RW
0 P37/INT0 input level selection
bit (Note 1) P36/INT1 input level selection 1 bit (Note 2) 2 P10, P12,P13 input level selection bit
0 0 0 0 0 0 0 0
3 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are "0".
4 5 6 7
Notes 1: For the 32-pin version, nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". 2: For the 32-pin and 36-pin versions, nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0".
Fig. 2.1.5 Structure of P1P3 control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A
16]
B
Name
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active
At reset
RW
0 INT0 interrupt edge
selection bit (Note 1) 1 INT1 interrupt edge selection bit ( Note 2)
0 0 0 0
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are "0".
3 4 Serial I/O1 or INT 1 interrupt
selection bit 0 : Serial I/O1 1 : INT1 0 : Timer X 5 Timer X or key-on wake up 1 : Key-on wake up interrupt selection bit Timer 2 or serial I/O2 interrupt 0 : Timer 2 6 selection bit 1 : Serial I/O2 CNTR0 or AD converter 0 : CNTR0 7 interrupt selection bit 1 : AD converter
0 0 0 0
Notes 1: 32-pin version: Not used. This is a write disabled bit. When this bit is read out, the value is "0". 2: 36-pin and 32-pin version: Not used. This is a write disabled bit. When this bit is read out, the value is "0".
Fig. 2.1.6 Structure of Interrupt edge selection register
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APPLICATION 7534 Group 2.1 I/O port
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C
16]
B 0 1
Name
UART receive/USBIN token interrupt request bit UART transmit/USBSETUP/ OUT token/Reset/Suspend/ Resume/INT1 interrupt request bit (Note 1) INT0 interrupt request bit (Note 2) Timer X or key-on wake up interrupt request bit
Function
0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
At reset
RW
0 0
2 3
4 Timer 1 interrupt request bit
request bit
0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
0 0 0 0 0 0
5 Timer 2 or serial I/O2 interrupt 0 : No interrupt request issued 6 CNTR0 or AD converter
interrupt request bit 7 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0".
: These bits can be cleared to "0" by program, but cannot be set. Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist. 2: 32-pin version: INT0 interrupt does not exist. This is a write disabled bit. When this bit is read out, the value is "0".
Fig. 2.1.7 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E
16]
B 0 1
Name
UART receive/USBIN token interrupt enable bit UART transmit/USBSETUP/ OUT token/Reset/Suspend/ Resume/INT1 interrupt enable bit (Note 1) INT0 interrupt enable bit (Note 2) Timer X or key-on wake up interrupt enable bit
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 0
2 3 4 5 6 7
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled Timer 1 interrupt enable bit 1 : Interrupt enabled Timer 2 or serial I/O2 interrupt 0 : Interrupt disabled enable bit 1 : Interrupt enabled 0 : Interrupt disabled CNTR0 or AD converter interrupt enable bit 1 : Interrupt enabled Nothing is allocated for this bit. Do not write "1" to this bit. When this bit is read out, the value is "0".
0 0 0 0 0 0
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist. 2: 32-pin version: INT0 interrupt does not exist. This is a write disabled bit. When this bit is read out, the value is "0".
Fig. 2.1.8 Structure of Interrupt control register 1
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APPLICATION 7534 Group 2.1 I/O port
2.1.3 Application example of key-on wake up Outline: The built-in pull-up resistor is used.
Pull-up control register (address 16 16)
b7 b0
PULL
111 P00 - P03 pull-up on
Interrupt edge selection register (address 3A 16)
b7 b0
INTEDGE
1 Timer X or key-on wake up interrupt selection : Key-on wake up selected
Interrupt control register 1 (address 3E 16)
b7 b0
ICON1
1 Timer X or key-on wake up interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7 b0
IREQ1
0 Timer X or key-on wake up interrupt request bit
Fig. 2.1.9 Relevant registers setting
7534 group
P03 P0i (i: 0 - 3) P02 Key ON P01
P00
Fig. 2.1.10 Application circuit example
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APPLICATION 7534 Group 2.1 I/O port
RESET
q : This bit is not used here. Set it to "0" or "1" arbitrary.
Initialization PULL ... Power down procedure INTEDGE (address 3A16), bit5 IREQ1 (address 3C16), bit3 ICON1 (address 3E16), bit3 WIT ... 1 0 1 *Key-on wake up selected *Clear the key-on wake up interrupt request bit to "0" *Key-on wake up interrupt enabled Key ON Process continuation Interrupt process of Key-on wake up ... ....... RTI ... (address 1616) XXXXX1112 *P03 - P00 pull-up On
Fig. 2.1.11 Control procedure 2.1.4 Handling of unused pins Table 2.1.1 Handling of unused pins Pins/Ports name Handling P0, P1, P2, P3, P4 *Set to the input mode and connect each to Vcc or Vss through a resistor of 1 k to 10 k. *Set to the output mode and open at "L" or "H" level. VREF XOUT *Connect to Vss (GND). *Open, only when using an external clock
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APPLICATION 7534 Group 2.1 I/O port
2.1.5 Notes on input and output pins (1) Notes in stand-by state In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O port "undefined". Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: * External circuit * Variation of output levels during the ordinary operation When using a built-in pull-up resistor, note on varied current values: * When setting as an input port : Fix its input level * When setting as an output port : Prevent current from flowing out to external. q Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are "undefined". This may cause power source current. * 1 stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. q Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. * As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing. * As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following : * Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. * As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : SEB, and CLB instructions
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APPLICATION 7534 Group 2.1 I/O port
2.1.6 Termination of unused pins (1) Terminate unused pins Output ports : Open Input ports : Connect each pin to VCC or VSS through each resistor of 1 k to 10 k. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. As for pins whose potential affects to operation modes such as pins CNVSS, INT or others, select the VCC pin or the VSS pin according to their operation mode. I/O ports : * Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 k to 10 k. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/ O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks Input ports and I/O ports : Do not open in the input mode. q Reason * The power source current may increase depending on the first-stage circuit. * An effect due to noise may be easily produced as compared with proper termination and shown on the above. I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. * At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
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APPLICATION 7534 Group 2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 Memory map
002816 002916 002A16 002B16 002C16 002D16 002E16
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS)
003A16 003C16
Interrupt edge selection register (INTEDGE)
Interrupt request register 1 (IREQ1)
003E16
Interrupt control register 1 (ICON1)
Fig. 2.2.1 Memory map of registers relevant to timers 2.2.2 Relevant registers
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12) [Address : 28 16] Prescaler X (PREX) [Address : 2C 16]
B
Function
At reset
RW
0 *Set a count value of each prescaler.
*The value set in this register is written to both each prescaler 1 and the corresponding prescaler latch at the same time. *When this register is read out, the count value of the corres2 ponding prescaler is read out.
1 1 1 1 1 1 1 1
3 4 5 6 7
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X
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APPLICATION 7534 Group 2.2 Timer
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 29 16]
B
Function
At reset
RW
0 *Set a count value of timer 1.
*The value set in this register is written to both timer 1 and timer 1 1 latch at the same time. *When this register is read out, the timer 1's count value is read 2 out.
1 0 0 0 0 0 0 0
3 4 5 6 7
Fig. 2.2.3 Structure of Timer 1
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address : 2A 16]
B
Function
At reset
RW
0 *Set a count value of timer 2.
*The value set in this register is written to both timer 2 and timer 2 latch at the same time. *When this register is read out, the timer 2's count value is read 2 out.
0 0 0 0 0 0 0 0
1
3 4 5 6 7
Fig. 2.2.4 Structure of Timer 2
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APPLICATION 7534 Group 2.2 Timer
Timer X
b7 b6 b5 b4 b3 b2 b1 b0 Timer X (TX) [Address : 2D 16]
B
Function
At reset
RW
0 *Set a count value of timer X.
*The value set in this register is written to both timer X and timer X 1 latch at the same time. *When this register is read out, the timer X's count value is read 2 out.
1 1 1 1 1 1 1 1
3 4 5 6 7
Fig. 2.2.5 Structure of Timer X
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APPLICATION 7534 Group 2.2 Timer
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TM) [Address : 2B 16]
B
Name
b1 b0
Function
0 0 1 1 0 : Timer mode 1 : Pulse output mode 0 : Event counter mode 1 : Pulse width measurement mode
At reset
RW
0 Timer X operating mode bits
0
1 2 CNTR0 active edge switch bit
0 0
The function depends on the operating mode. (Refer to Table 2.2.1) 0 : Count start 1 : Count stop
3 Timer X count stop bit
0 0 0 0 0
4 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are "0".
5 6 7
Fig. 2.2.6 Structure of Timer X mode register Table 2.2.1 CNTR0 active edge switch bit function Timer X operation modes Timer mode CNTR0 active edge switch bit (bit 2 of address 2B16) contents "0" CNTR0 interrupt request occurrence: Falling edge ; No influence to timer count "1" CNTR0 interrupt request occurrence: Rising edge ; No influence to timer count Pulse output mode "0" Pulse output start: Beginning at "H" level CNTR0 interrupt request occurrence: Falling edge "1" Pulse output start: Beginning at "L" level CNTR0 interrupt request occurrence: Rising edge Event counter mode "0" Timer X: Rising edge count CNTR0 interrupt request occurrence: Falling edge "1" Timer X: Falling edge count Pulse width measurement mode CNTR0 interrupt request occurrence: Rising edge "0" Timer X: "H" level width measurement CNTR0 interrupt request occurrence: Falling edge "1" Timer X: "L" level width measurement CNTR0 interrupt request occurrence: Rising edge
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APPLICATION 7534 Group 2.2 Timer
Timer count source set register
b7 b6 b5 b4 b3 b2 b1 b0 Timer count source set register (TCSS) [Address : 2E
16]
B
Name
selection bit (Note)
Function
0 : f(XIN) / 16 1 : f(XIN) / 2
At reset
RW
0 Timer X count source
0 0 0 0 0 0 0 0
1 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are "0".
2 3 4 5 6 7
Note: To switch the timer X count source selection bit, stop the timer X count operation before do that.
Fig. 2.2.7 Structure of Timer count source set register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A
16]
B
Name
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active
At reset
RW
0 INT0 interrupt edge selection bit (Note 1) 1 INT1 interrupt edge selection bit ( Note 2)
0 0 0 0
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are "0".
3 4 Serial I/O1 or INT 1 interrupt
selection bit 0 : Serial I/O1 1 : INT1 0 : Timer X 5 Timer X or key-on wake up 1 : Key-on wake up interrupt selection bit Timer 2 or serial I/O2 interrupt 0 : Timer 2 6 selection bit 1 : Serial I/O2 0 : CNTR0 7 CNTR0 or AD converter interrupt selection bit 1 : AD converter
0 0 0 0
Notes 1: 32-pin version: Not used. This is a write disabled bit. When this bit is read out, the value is "0". 2: 36-pin and 32-pin version: Not used. This is a write disabled bit. When this bit is read out, the value is "0".
Fig. 2.2.8 Structure of Interrupt edge selection register
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APPLICATION 7534 Group 2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C
16]
B 0 1
Name
UART receive/USBIN token interrupt request bit UART transmit/USBSETUP/ OUT token/Reset/Suspend/ Resume/INT1 interrupt request bit (Note 1) INT0 interrupt request bit (Note 2) Timer X or key-on wake up interrupt request bit
Function
0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
At reset
RW
0 0
2 3
4 Timer 1 interrupt request bit
request bit
0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
0 0 0 0 0 0
5 Timer 2 or serial I/O2 interrupt 0 : No interrupt request issued 6 CNTR0 or AD converter
interrupt request bit 7 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0".
: These bits can be cleared to "0" by program, but cannot be set. Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist. 2: 32-pin version: INT0 interrupt does not exist. This is a write disabled bit. When this bit is read out, the value is "0".
Fig. 2.2.9 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E
16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 UART receive/USBIN token
interrupt enable bit 1 UART transmit/USBSETUP/ OUT token/Reset/Suspend/ Resume/INT1 interrupt enable bit (Note 1) 2 INT0 interrupt enable bit (Note 2) 3 Timer X or key-on wake up interrupt enable bit
0 0
4 5 6 7
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled Timer 1 interrupt enable bit 1 : Interrupt enabled Timer 2 or serial I/O2 interrupt 0 : Interrupt disabled enable bit 1 : Interrupt enabled 0 : Interrupt disabled CNTR0 or AD converter interrupt enable bit 1 : Interrupt enabled Nothing is allocated for this bit. Do not write "1" to this bit. When this bit is read out, the value is "0".
0 0 0 0 0 0
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist. 2: 32-pin version: INT0 interrupt does not exist. This is a write disabled bit. When this bit is read out, the value is "0".
Fig. 2.2.10 Structure of Interrupt control register 1
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APPLICATION 7534 Group 2.2 Timer
2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer 1, Timer 2) When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
